Computer Fundamentals and Computer Architecture
Core concepts
Candidates must be fluent in number systems and data representation (binary, octal, hex, two's complement, BCD, ASCII/Unicode), logic gates and Boolean algebra, and the fetch-decode-execute cycle. Know the roles of the program counter, instruction register, memory address register, accumulator, and control unit. Understand the memory hierarchy (registers, cache, RAM, secondary storage) with its speed-cost-capacity trade-offs, and the distinction between RISC and CISC, von Neumann and Harvard architectures, and direct versus associative cache mapping. Be clear about bus types (address, data, control), interrupts, and pipelining hazards.
Traps
Questions often test the range of two's complement (an n-bit signed integer spans -2^(n-1) to 2^(n-1)-1), the difference between a bit and a byte, and the fact that hexadecimal is only a compact notation, not a separate machine representation. Another common trap: conflating clock speed with throughput, or assuming cache increases main memory capacity. Watch for questions that ask which register holds the address of the next instruction (PC) versus the instruction itself (IR).
Worked example
Represent -5 in 8-bit two's complement. Write +5 as 0000 0101, invert to 1111 1010, add 1 to get 1111 1011. Check: the leading 1 signals negative, and the value is -128 + 64 + 32 + 16 + 8 + 2 + 1 = -5. Rule of thumb: invert-and-add-one always yields the correct two's complement, and the same bit pattern can be read as unsigned 251, so always state the interpretation.