Computer architecture and hardware
Computer architecture and hardware
This domain examines the stored-program machine: how instructions and data share one memory, how the processor fetches and executes them, and how the memory hierarchy and instruction-set design affect performance.
The von Neumann model
Instructions and data share one memory and one set of buses. The address bus is unidirectional and its width fixes addressable memory: n lines give 2ⁿ locations. The data bus is bidirectional and its width fixes the word moved per transfer. The control bus carries read/write, clock and interrupt signals.
Registers and the fetch–decode–execute cycle
- PC holds the address of the next instruction; MAR holds the address currently being accessed.
- MDR holds the data or instruction just read, or about to be written; CIR holds the instruction being executed.
- ACC is the accumulator; the ALU performs arithmetic and logic; the CU decodes and issues control signals.
- Interrupts are checked at the end of an instruction; current state is pushed to the stack and the ISR address loaded into the PC.
Improving performance
Pipelining overlaps fetch, decode and execute for consecutive instructions. Cache exploits temporal and spatial locality to cut average memory access time. RISC uses simple fixed-length instructions and many registers, so it pipelines well but needs more instructions; CISC uses variable-length, complex instructions that do more per instruction.
Worked example
A processor has a 20-bit address bus and 16-bit data bus. How much memory can it address, and what happens when it executes LDA 300?
Addressable memory = 2²⁰ = 1,048,576 locations = 1 MiB, each 16 bits wide. During fetch the PC contents go to the MAR, memory returns the instruction to the MDR and it is copied to the CIR; the PC increments. During execute, address 300 goes to the MAR, the operand is read into the MDR and loaded into the ACC. STA 302 reverses this, sending the ACC value through the MDR to address 302.
Traps that cost marks
- Saying the MAR holds the instruction; it holds an address, and the CIR holds the instruction.
- Forgetting that the PC increments during fetch, before execution.
- Confusing cache (hardware-managed, transparent) with virtual memory (disk-backed, causes page faults).
- Claiming RISC programs always execute fewer instructions.
- Misstating bus direction: address out only, data both ways.