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Cameroon GCE A-Level Computer Science - independent foundations study materials
Cameroon GCE A-Level Computer Science - independent foundations study resources

Cameroon GCE A-Level Computer Science - independent foundations practice questions

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Question 1Algorithms and computational thinking

A 2D array `Table[0..4][0..9]` (5 rows by 10 columns) is stored in row-major order starting at base memory address 1000. If each element occupies 4 bytes of memory, what is the memory address of element `Table[3][7]`?

  1. 1128
  2. 1148 Correct answer.
  3. 1152
  4. 1188

Explanation

In row-major order for 0-indexed arrays, the address formula is: `Address = Base + ((RowIndex * NumColumns) + ColIndex) * ElementSize`. Here, RowIndex = 3, ColIndex = 7, NumColumns = 10, and ElementSize = 4 bytes. Calculation: `Address = 1000 + ((3 * 10) + 7) * 4 = 1000 + (37 * 4) = 1000 + 148 = 1148`.

Question 2Algorithms and computational thinking

In a standard singly linked list containing n nodes with only a `head` pointer, what are the worst-case time complexities for inserting a node at the head and deleting the last node (tail), respectively?

  1. O(1) for head insertion and O(1) for tail deletion
  2. O(1) for head insertion and O(n) for tail deletion Correct answer.
  3. O(n) for head insertion and O(1) for tail deletion
  4. O(n) for head insertion and O(n) for tail deletion

Explanation

Inserting at the head requires updating the new node's next pointer and the head pointer, taking constant time O(1). Deleting the tail node requires traversing from the head through all n nodes to locate the second-to-last node (to set its next pointer to NULL), which requires linear time O(n).

Question 3Algorithms and computational thinking

To insert a new node `newNode` between existing adjacent nodes `prevNode` and `currNode` in a doubly linked list, which sequence of pointer assignments is correct?

  1. newNode.next = currNode; newNode.prev = prevNode; prevNode.next = newNode; currNode.prev = newNode; Correct answer.
  2. prevNode.next = currNode; currNode.prev = prevNode; newNode.next = prevNode; newNode.prev = currNode;
  3. newNode.prev = currNode; newNode.next = prevNode; currNode.next = newNode; prevNode.prev = newNode;
  4. currNode.prev = newNode; prevNode.next = currNode; newNode.next = prevNode; newNode.prev = currNode;

Explanation

First, the new node's forward and backward links are established (`newNode.next = currNode; newNode.prev = prevNode;`). Then, the surrounding nodes are linked to the new node (`prevNode.next = newNode; currNode.prev = newNode;`). This correctly splices the node into the doubly linked list without losing pointer references.

Question 4Algorithms and computational thinking

What is the correct postfix (Reverse Polish Notation) equivalent of the infix arithmetic expression: `(A + B) * (C - D) / E`?

  1. A B + C D - * E / Correct answer.
  2. A B + * C D - / E
  3. * + A B - C D / E
  4. A B C D + - * E /

Explanation

Using operator precedence and associativity: `(A + B)` converts to `A B +`. `(C - D)` converts to `C D -`. Multiplying these two sub-expressions yields `A B + C D - *`. Finally, dividing by E yields `A B + C D - * E /`.

Question 5Algorithms and computational thinking

Evaluate the following postfix arithmetic expression using a stack: `6 3 2 + * 10 -`. What is the final evaluated result?

  1. 10
  2. 18
  3. 20 Correct answer.
  4. 28

Explanation

Stack evaluation trace: Push 6, push 3, push 2. Read `+`: pop 2 and 3, compute 3 + 2 = 5, push 5 (stack: [6, 5]). Read `*`: pop 5 and 6, compute 6 * 5 = 30, push 30 (stack: [30]). Push 10 (stack: [30, 10]). Read `-`: pop 10 and 30, compute 30 - 10 = 20, push 20. Final result = 20.

Question 6Algorithms and computational thinking

In a circular queue implemented using a fixed-size array of capacity N, where `front` indicates the head element and `rear` indicates the last inserted item, how is the queue full condition correctly expressed?

  1. rear == N - 1
  2. (rear + 1) % N == front Correct answer.
  3. rear == front
  4. front == (rear + N) / 2

Explanation

In a circular queue utilizing modulo arithmetic to wrap around the array boundaries, one slot is typically left vacant to distinguish between an empty and full queue. The queue is full when advancing `rear` by one position meets `front`: `(rear + 1) % N == front`.

Question 7Algorithms and computational thinking

In a full binary tree where every internal node has exactly two children, if the height of the tree is h (with the root node alone at height 0), what is the maximum number of leaf nodes?

  1. 2^h Correct answer.
  2. 2^(h+1) - 1
  3. 2h + 1
  4. h^2

Explanation

At depth 0 (root), there is 2^0 = 1 node. At depth 1, there are 2^1 = 2 nodes. By induction, at height h (the bottom level), the maximum number of leaf nodes is 2^h. (The total number of nodes across the entire tree would be 2^(h+1) - 1).

Question 8Algorithms and computational thinking

Performing an in-order (Left-Root-Right) traversal on a valid Binary Search Tree (BST) containing unique keys always visits the keys in which order?

  1. Strictly descending order
  2. Strictly ascending (sorted) order Correct answer.
  3. Topological dependency order
  4. Level-by-level breadth-first order

Explanation

By definition of a Binary Search Tree, all keys in the left subtree are smaller than the root, and all keys in the right subtree are greater than the root. Traversing Left, then Root, then Right recursively guarantees that nodes are visited in strictly ascending numerical/alphabetical sorted order.

Question 9Algorithms and computational thinking

When deleting a node that has two non-empty children from a Binary Search Tree, how is the node replaced to preserve the BST invariant?

  1. Replace the node with the maximum element of the right subtree or minimum element of the left subtree.
  2. Replace the node with either its in-order successor (minimum key in the right subtree) or in-order predecessor (maximum key in the left subtree), then delete that successor/predecessor node. Correct answer.
  3. Replace the node with the tree root and rebalance using AVL rotations.
  4. Delete both children subtrees completely and promote the left child's right grandchild to the current position.

Explanation

To maintain the BST ordering property, a node with two children must be replaced by the value closest to it in sorted order: either its in-order successor (the leftmost/minimum node in its right subtree) or in-order predecessor (the rightmost/maximum node in its left subtree). The chosen successor/predecessor is then deleted from its original leaf/single-child position.

Question 10Algorithms and computational thinking

A binary tree produces the Pre-order traversal `[A, B, D, E, C, F]` and the In-order traversal `[D, B, E, A, F, C]`. What is the Post-order traversal of this binary tree?

  1. `[D, E, B, F, C, A]` Correct answer.
  2. `[D, E, F, B, C, A]`
  3. `[D, B, E, F, C, A]`
  4. `[E, D, B, C, F, A]`

Explanation

From Pre-order, A is the root. In In-order `[D, B, E, A, F, C]`, the left subtree contains `{D, B, E}` and the right subtree contains `{F, C}`. In the left subtree, Pre-order is `[B, D, E]` and In-order is `[D, B, E]`, so B is root with left child D and right child E. In the right subtree, Pre-order is `[C, F]` and In-order is `[F, C]`, so C is root with left child F. Post-order (Left-Right-Root): Left subtree = `D, E, B`; Right subtree = `F, C`; Root = `A`. Combined: `[D, E, B, F, C, A]`.

Question 11Algorithms and computational thinking

For a sparse graph with V vertices and E edges where E << V^2, why is an Adjacency List representation generally preferred over an Adjacency Matrix?

  1. Adjacency lists require O(V^2) memory space and allow O(1) edge existence checks between any two vertices.
  2. Adjacency lists require O(V + E) memory space and allow efficient iteration over adjacent vertices, compared to O(V^2) space for an adjacency matrix. Correct answer.
  3. Adjacency lists eliminate pointer overhead and store all edges in contiguous hardware registers.
  4. Adjacency matrices cannot represent weighted or directed edges.

Explanation

An Adjacency Matrix always allocates a V x V matrix requiring O(V^2) space regardless of how few edges exist. In a sparse graph, an Adjacency List uses only O(V + E) memory by storing linked lists/dynamic arrays of actual outgoing edges, saving significant memory and speeding up vertex neighborhood iterations.

Question 12Algorithms and computational thinking

Which abstract data structure is fundamentally used in Breadth-First Search (BFS) on an unweighted graph to guarantee finding the shortest path (minimum edge count) from a source vertex?

  1. Stack (LIFO)
  2. Queue (FIFO) Correct answer.
  3. Priority Queue (Min-Heap)
  4. Binary Search Tree

Explanation

Breadth-First Search uses a First-In, First-Out (FIFO) Queue. By visiting and enqueuing all immediate neighbors at distance d before examining vertices at distance d+1, BFS explores the graph layer by layer, ensuring that the first time a target vertex is dequeued, the shortest path in an unweighted graph has been found.

Question 13Algorithms and computational thinking

During a Depth-First Search (DFS) traversal of a directed graph using 3-color vertex marking (White = unvisited, Gray = currently on recursion stack, Black = finished), how is a directed cycle detected?

  1. When an outgoing edge encounters an unvisited White vertex.
  2. When an outgoing edge encounters a currently active Gray vertex on the recursion stack (a back edge). Correct answer.
  3. When an outgoing edge encounters a completely processed Black vertex (a cross edge).
  4. When the recursion stack becomes empty before all vertices have been visited.

Explanation

A directed graph contains a cycle if and only if DFS discovers a back edge pointing to an ancestor currently on the active recursion call stack. In standard 3-color DFS algorithms, active ancestors are marked Gray; encountering a Gray vertex confirms a closed cycle.

Question 14Algorithms and computational thinking

Under which condition will Dijkstra's single-source shortest path algorithm fail to produce correct shortest-path distances?

  1. When the graph is a Directed Acyclic Graph (DAG).
  2. When the graph contains edges with negative weights. Correct answer.
  3. When the graph contains disconnected components.
  4. When multiple distinct paths have identical total weights.

Explanation

Dijkstra's algorithm operates on a greedy principle: once a vertex is marked as visited/settled, its recorded distance is assumed to be final and minimal. If edges have negative weights, a future path could reduce the cost to an already-settled vertex, violating Dijkstra's greedy invariant (the Bellman-Ford algorithm must be used instead).

Question 15Algorithms and computational thinking

What is the fundamental algorithmic difference between Kruskal's algorithm and Prim's algorithm for finding a Minimum Spanning Tree (MST)?

  1. Kruskal's algorithm grows a single tree outward from a starting root vertex, while Prim's processes all edges globally.
  2. Kruskal's algorithm sorts all edges globally and adds the lightest edge that does not form a cycle (using Disjoint Sets), whereas Prim's grows a single connected tree vertex by vertex from an arbitrary start. Correct answer.
  3. Prim's algorithm only works on directed graphs, whereas Kruskal's algorithm is restricted to planar bipartite graphs.
  4. Kruskal's algorithm produces an optimal MST while Prim's only produces a heuristic approximation.

Explanation

Kruskal's algorithm takes an edge-centric approach: it sorts all E edges by weight and uses a Union-Find (Disjoint Set) data structure to greedily add edges across the whole graph that do not create cycles. Prim's algorithm is vertex-centric: it maintains a growing single tree and greedily adds the minimum-weight cut edge connecting a tree vertex to a non-tree vertex.

Question 16Algorithms and computational thinking

What is the maximum number of key comparisons required to search for a target element in a sorted array of 1,000,000 items using Binary Search?

  1. 20 comparisons Correct answer.
  2. 100 comparisons
  3. 500,000 comparisons
  4. 1,000,000 comparisons

Explanation

Binary search has a worst-case time complexity of O(log2(n)). For n = 1,000,000: since 2^19 = 524,288 and 2^20 = 1,048,576, the maximum number of iterations/comparisons is ceil(log2(1,000,000)) = 20.

Question 17Algorithms and computational thinking

What is the exact number of key comparisons performed by standard Bubble Sort when sorting an array of n elements initially arranged in reverse sorted order?

  1. n - 1
  2. n * log2(n)
  3. (n * (n - 1)) / 2 Correct answer.
  4. n^2 + n

Explanation

On pass 1, Bubble Sort makes (n - 1) comparisons; on pass 2, it makes (n - 2); continuing down to 1 comparison on pass (n - 1). Summing the arithmetic series: (n - 1) + (n - 2) + ... + 1 = n(n - 1) / 2 comparisons, which is O(n^2).

Question 18Algorithms and computational thinking

Why is Insertion Sort particularly efficient for datasets that are already nearly or fully sorted?

  1. It partitions the data using a divide-and-conquer strategy requiring O(log n) auxiliary stack space.
  2. Each element needs to be compared only once against its immediate predecessor, yielding an optimal linear O(n) best-case execution time. Correct answer.
  3. It transforms the input array into a balanced binary heap in O(1) time.
  4. It automatically runs in O(n log n) time regardless of the initial permutation of the array.

Explanation

In Insertion Sort, each element is shifted into its correct position among already-sorted predecessors. If the array is already sorted, the inner loop terminates immediately after a single comparison (since array[j] >= array[j-1]), performing exactly n - 1 comparisons with 0 data shifts, resulting in O(n) linear time.

Question 19Algorithms and computational thinking

Given the recurrence relation T(n) = 2T(n/2) + O(n) for Merge Sort, what are its guaranteed worst-case time complexity and auxiliary space complexity when sorting an array of n elements?

  1. Time: O(n^2), Space: O(1)
  2. Time: O(n log n), Space: O(n) Correct answer.
  3. Time: O(n log n), Space: O(1)
  4. Time: O(log n), Space: O(n)

Explanation

By Case 2 of the Master Theorem for T(n) = 2T(n/2) + O(n), the recursion tree has log2(n) levels with O(n) work per level, guaranteeing O(n log n) time complexity across all cases (best, average, worst). Merging two sorted subarrays requires an auxiliary buffer array of size n, giving O(n) auxiliary space complexity.

Question 20Algorithms and computational thinking

In a standard Quick Sort implementation that always selects the first element as the pivot, what causes the time complexity to degrade from O(n log n) to O(n^2)?

  1. The array elements are uniformly distributed without duplicates.
  2. The input array is already completely sorted (or reverse sorted), resulting in maximally unbalanced partitions of sizes 0 and n - 1 at each recursive level. Correct answer.
  3. The recursion uses tail call optimization to eliminate auxiliary call stack frames.
  4. The partitioning routine swaps non-adjacent elements using Hoare's two-pointer method.

Explanation

When the pivot is the first element and the array is already sorted, the pivot is always the smallest element. Partitioning splits the array into a subarray of 0 elements and a subarray of n - 1 elements. This produces n recursive levels with O(n) work per level, causing quadratic O(n^2) degradation.

Question 21Algorithms and computational thinking

What is the Big-O time complexity of the following nested loop code fragment? ``` int sum = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= i; j++) { sum += j; } } ```

  1. O(n)
  2. O(n log n)
  3. O(n^2) Correct answer.
  4. O(2^n)

Explanation

The outer loop runs n times. For each iteration i, the inner loop executes i times. The total number of inner loop executions is the sum: 1 + 2 + 3 + ... + n = n(n + 1) / 2 = (n^2 + n) / 2. Dropping lower-order terms and constant factors yields O(n^2).

Question 22Algorithms and computational thinking

What is the Big-O time complexity of an algorithm whose loop control variable doubles on each iteration, as in: `for (int k = 1; k < n; k = k * 2) { doWork(k); }` where `doWork()` runs in O(1) time?

  1. O(1)
  2. O(log n) Correct answer.
  3. O(n)
  4. O(n^2)

Explanation

In each step, k takes values 1, 2, 4, 8, ..., 2^m. The loop terminates when 2^m >= n, which implies m = log2(n) iterations. Since each iteration performs O(1) work, the total time complexity is O(log n).

Question 23Algorithms and computational thinking

What is the maximum auxiliary call stack space complexity of the naive recursive Fibonacci algorithm: `int fib(int n) { if (n <= 1) return n; return fib(n-1) + fib(n-2); }`?

  1. O(1)
  2. O(n) Correct answer.
  3. O(n^2)
  4. O(2^n)

Explanation

Although the naive recursive Fibonacci algorithm makes O(2^n) total calls (exponential time complexity), the maximum depth of the call stack at any single instant corresponds to the longest branch in the recursion tree, which is fib(n) -> fib(n-1) -> ... -> fib(1), requiring at most O(n) activation records on the stack.

Question 24Algorithms and computational thinking

What severe runtime error invariably occurs if a recursive function is executed without a properly defined base case termination condition?

  1. The operating system terminates the process due to a Stack Overflow (call stack exhaustion). Correct answer.
  2. The compiler converts the recursive function into an infinite hardware interrupt.
  3. Variable values automatically wrap around to negative infinity without memory consumption.
  4. The runtime environment converts the recursive function into an iterative loop automatically.

Explanation

Every recursive call allocates an activation frame (return address, local variables, parameters) on the call stack. Without a valid base case, the function calls itself indefinitely until the allocated thread call stack memory is completely exhausted, triggering a fatal Stack Overflow runtime crash.

Question 25Algorithms and computational thinking

Why can an optimizing compiler execute a tail-recursive function in O(1) auxiliary call stack space instead of O(n)?

  1. Because tail-recursive functions store all variable values in permanent static CPU registers.
  2. Because the recursive call is the absolute final operation before returning, allowing the compiler to reuse the current stack frame rather than allocating a new one. Correct answer.
  3. Because tail recursion evaluates arithmetic expressions using bitwise shift operators.
  4. Because the compiler automatically offloads tail-recursive calls to asynchronous background threads.

Explanation

In a tail-recursive function, there is no remaining work to perform after the recursive call returns. Under Tail Call Optimization (TCO), the compiler simply overwrites the parameters in the existing stack frame and jumps back to the beginning of the function, effectively converting the recursion into an iterative loop with O(1) stack space.

Question 26Computer architecture, operating systems and networks

In computer processor architecture, what is the defining structural difference between the Harvard architecture and the Von Neumann architecture?

  1. Harvard architecture uses physically separate memory units and buses for instructions and data, whereas Von Neumann uses unified memory and buses for both. Correct answer.
  2. Von Neumann architecture utilizes separate arithmetic pipelines for integer and floating-point operations, whereas Harvard combines them.
  3. Harvard architecture requires all instructions to execute in a single clock cycle, whereas Von Neumann uses multi-cycle microcode.
  4. Von Neumann architecture uses direct-mapped caches exclusively, whereas Harvard architecture supports fully associative caches.

Explanation

Harvard architecture incorporates physically distinct storage and signal pathways (buses) for instructions and data, allowing simultaneous instruction fetch and data read/write. In contrast, Von Neumann architecture uses a unified memory space and shared system bus for both instructions and data, which can create a data transfer bottleneck known as the Von Neumann bottleneck.

Question 27Computer architecture, operating systems and networks

During the CPU fetch-decode-execute cycle, what is the primary role of the Program Counter (PC)?

  1. It holds the current machine instruction being decoded and executed by the Control Unit.
  2. It stores the memory address of the next instruction to be fetched and executed. Correct answer.
  3. It records arithmetic status flags such as zero, carry, sign, and overflow resulting from ALU operations.
  4. It temporarily stores operand data transferred between main memory and the Arithmetic Logic Unit.

Explanation

The Program Counter (PC), also called the Instruction Pointer, holds the memory address of the next sequential instruction to be fetched from memory. Once the address is copied to the Memory Address Register (MAR), the PC is automatically incremented or updated to a branch target.

Question 28Computer architecture, operating systems and networks

During a memory read operation in the fetch cycle, how do the Memory Address Register (MAR) and Memory Data Register (MDR) interact with the system buses?

  1. MAR places data onto the data bus while MDR receives the target address from the address bus.
  2. MAR holds the address placed onto the address bus, while MDR latches the data returned from memory via the data bus. Correct answer.
  3. MAR decodes the operation code while MDR sends control signals over the control bus to synchronize RAM.
  4. Both MAR and MDR send parallel 64-bit addresses over the address bus to achieve interleaved memory access.

Explanation

The MAR is directly connected to the unidirectional address bus and holds the physical memory location to be accessed. The MDR (or Memory Buffer Register) is connected to the bidirectional data bus and holds the data word or instruction fetched from that memory address.

Question 29Computer architecture, operating systems and networks

In a standard accumulator-based CPU architecture, which sequence of Register Transfer Level (RTL) micro-operations correctly represents the instruction fetch phase?

  1. MAR <- [PC]; PC <- [PC] + 1; MDR <- Memory[MAR]; CIR <- [MDR] Correct answer.
  2. MDR <- [PC]; MAR <- [MDR]; CIR <- Memory[MAR]; PC <- [PC] + 1
  3. CIR <- [PC]; MAR <- [CIR]; MDR <- Memory[MAR]; PC <- [MDR]
  4. MAR <- [ACC]; MDR <- Memory[MAR]; PC <- [PC] + 1; CIR <- [MDR]

Explanation

The fetch phase begins by transferring the address from the PC into the MAR (`MAR <- [PC]`). Simultaneously or immediately after, the PC is incremented (`PC <- [PC] + 1`), the instruction word is read from memory into the MDR (`MDR <- Memory[MAR]`), and finally the instruction is copied into the Current Instruction Register (`CIR <- [MDR]`) for decoding.

Question 30Computer architecture, operating systems and networks

A processor has a 32-bit address bus and byte-addressable physical memory. What is the maximum physical memory capacity that this processor can directly address?

  1. 512 Megabytes (512 MB)
  2. 2 Gigabytes (2 GB)
  3. 4 Gigabytes (4 GB) Correct answer.
  4. 16 Gigabytes (16 GB)

Explanation

With an n-bit address bus, a processor can address 2^n unique memory locations. For a 32-bit address bus, 2^32 = 4,294,967,296 distinct byte addresses, which equals exactly 4 Gigabytes (4 GB) of addressable memory.

Question 31Computer architecture, operating systems and networks

A computer system uses 16-bit byte-level memory addresses and a direct-mapped cache of 4 KB total data capacity with 64-byte cache blocks (lines). How are the 16 address bits partitioned into Tag, Line Index, and Block Offset fields?

  1. Tag = 4 bits, Line Index = 6 bits, Block Offset = 6 bits Correct answer.
  2. Tag = 6 bits, Line Index = 6 bits, Block Offset = 4 bits
  3. Tag = 5 bits, Line Index = 6 bits, Block Offset = 5 bits
  4. Tag = 6 bits, Line Index = 4 bits, Block Offset = 6 bits

Explanation

With 64-byte blocks, the Block Offset requires log2(64) = 6 bits. The cache has 4 KB / 64 B = 4096 / 64 = 64 lines (slots), requiring log2(64) = 6 bits for the Line Index. The remaining bits form the Tag: 16 - (6 + 6) = 4 bits. Thus: Tag = 4 bits, Index = 6 bits, Offset = 6 bits.

Question 32Computer architecture, operating systems and networks

What is the principal operational reason that Static RAM (SRAM) is used for CPU cache memory while Dynamic RAM (DRAM) is used for main system memory?

  1. SRAM uses capacitor storage requiring periodic refresh cycles, offering very high density at low cost.
  2. SRAM uses flip-flop latch circuits that retain data without refreshing, providing faster access times despite lower density and higher cost per bit. Correct answer.
  3. DRAM retains its state indefinitely without electrical power, making it ideal for persistent operating system loading.
  4. DRAM operates synchronously with the system bus clock whereas SRAM operates purely asynchronously without clock signals.

Explanation

SRAM utilizes multi-transistor flip-flops (typically 6 transistors per cell) to store each bit. Because it does not rely on leaking capacitors, it requires no refresh circuitry, achieving nanosecond access times suitable for L1/L2 caches, whereas DRAM uses single-transistor/capacitor cells that are cheaper and denser for large main memory.

Question 33Computer architecture, operating systems and networks

In a virtual memory system using demand paging, what primary condition causes severe thrashing to occur?

  1. The Translation Lookaside Buffer (TLB) reaches full capacity and stops caching page table entries.
  2. The sum of the working sets of active processes exceeds available physical RAM frames, causing the OS to spend more time swapping pages than executing instructions. Correct answer.
  3. The operating system scheduler assigns equal CPU time slices to I/O-bound and CPU-bound processes.
  4. The CPU executes non-maskable hardware interrupts faster than the disk controller can service them.

Explanation

Thrashing occurs when the resident memory is insufficient to hold the active working sets of all executing processes. As a result, page faults occur continuously, and the CPU spends virtually all its time waiting for high-latency disk paging operations rather than executing user instructions.

Question 34Computer architecture, operating systems and networks

In a pipelined CPU, which type of hazard occurs when an instruction depends on the data result of an immediately preceding instruction that has not yet completed its write-back stage?

  1. Structural hazard
  2. Control hazard (branch hazard)
  3. Data hazard (Read-After-Write) Correct answer.
  4. Arbitration hazard

Explanation

A data hazard (specifically Read-After-Write or RAW) occurs when an instruction in the decode or execute stage requires an operand value that is currently being computed by an earlier instruction in the pipeline before it has been written back to the register file.

Question 35Computer architecture, operating systems and networks

Which architectural characteristic is fundamentally distinctive of Reduced Instruction Set Computers (RISC) compared to Complex Instruction Set Computers (CISC)?

  1. RISC relies heavily on variable-length instructions with complex memory-to-memory addressing modes.
  2. RISC utilizes fixed-length single-cycle instructions with a load-store architecture and extensive general-purpose registers. Correct answer.
  3. CISC processors eliminate microcode and execute all operations directly in hardwired control logic.
  4. RISC designs incorporate specialized hardware instructions for high-level language loops and polynomial evaluation.

Explanation

RISC architectures emphasize simple, fixed-length instructions that execute in a single clock cycle, utilizing a load-store model where memory access is strictly isolated to explicit LOAD and STORE instructions, operating primarily on a large register set.

Question 36Computer architecture, operating systems and networks

In an assembly language instruction, a base memory address of 2000 is specified and the Index Register (IX) contains the value 48. If indexed addressing mode is used, what is the effective memory address accessed?

  1. Memory address 48
  2. Memory address 1952
  3. Memory address 2048 Correct answer.
  4. Memory address 96000

Explanation

In indexed addressing mode, the effective address (EA) is calculated by adding the contents of the specified Index Register to the base address given in the instruction operand: EA = Base Address + [IX] = 2000 + 48 = 2048.

Question 37Computer architecture, operating systems and networks

How does a standard two-pass assembler resolve forward label references in an assembly language source program?

  1. Pass 1 executes the program speculatively, while Pass 2 rolls back invalid branch targets.
  2. Pass 1 scans the source code to construct the symbol table mapping labels to memory addresses; Pass 2 uses the symbol table to generate object machine code. Correct answer.
  3. Pass 1 replaces all labels with dynamic runtime pointers, while Pass 2 delegates address resolution to the interpreter.
  4. Pass 1 performs macro expansion and syntax checking; Pass 2 allocates dynamic RAM heap space for local variables.

Explanation

In a two-pass assembler, Pass 1 increments a Location Counter (LC) to determine the size of each instruction and builds a Symbol Table recording the assigned memory addresses of all labels. Pass 2 re-reads the source code, translates mnemonics to opcodes, and substitutes label names with their exact numeric addresses from the Symbol Table.

Question 38Computer architecture, operating systems and networks

What is the 8-bit Two's complement binary representation of the decimal integer -45?

  1. 11010011 Correct answer.
  2. 10101101
  3. 11010010
  4. 10110011

Explanation

To find -45 in 8-bit Two's complement: Positive 45 in binary is `00101101`. Inverting all bits (One's complement) gives `11010010`. Adding 1 yields `11010011`. Verification: -128 + 64 + 16 + 2 + 1 = -45.

Question 39Computer architecture, operating systems and networks

In the IEEE 754 single-precision 32-bit floating-point standard (1 sign bit, 8 exponent bits with bias 127, 23 mantissa bits), what is the decimal equivalent of the hexadecimal word 0x40C00000?

  1. 3.0
  2. 6.0 Correct answer.
  3. 12.0
  4. 24.0

Explanation

Hex `0x40C00000` in binary is `0100 0000 1100 0000 0000 0000 0000 0000`. Sign bit = 0 (positive). Exponent field = `10000001` (binary 129 in decimal). True exponent = 129 - 127 = 2. Mantissa bits = `100...000` (fraction 0.5), yielding normalized significand 1.100...2 = 1.5 in decimal. Value = +1 * 1.5 * 2^2 = 1.5 * 4 = 6.0.

Question 40Computer architecture, operating systems and networks

Why has the Unicode UTF-8 encoding standard largely superseded 7-bit ASCII in modern software applications?

  1. UTF-8 encodes every character using exactly 8 bits, completely eliminating multi-byte processing overhead.
  2. UTF-8 provides a variable-length encoding (1 to 4 bytes) that is backwards-compatible with ASCII while supporting over 1.1 million international characters. Correct answer.
  3. ASCII cannot represent standard uppercase English letters or mathematical digits.
  4. UTF-8 automatically encrypts textual streams using public-key cryptography.

Explanation

UTF-8 uses 1 byte for standard ASCII characters (0–127), ensuring complete backwards compatibility with legacy ASCII software, while scaling up to 4 bytes to represent virtually all living human languages, mathematical symbols, and emojis in the Unicode standard.

Question 41Computer architecture, operating systems and networks

Simplify the Boolean expression F = NOT((A + B) . NOT(C)) using De Morgan's laws and Boolean identities.

  1. F = (NOT(A) . NOT(B)) + C Correct answer.
  2. F = (NOT(A) + NOT(B)) . C
  3. F = (A . B) + NOT(C)
  4. F = NOT(A) + NOT(B) + NOT(C)

Explanation

Applying De Morgan's law NOT(X . Y) = NOT(X) + NOT(Y) where X = (A + B) and Y = NOT(C): F = NOT(A + B) + NOT(NOT(C)). Applying De Morgan's law to the first term gives NOT(A + B) = NOT(A) . NOT(B), and double negation gives NOT(NOT(C)) = C. Therefore, F = (NOT(A) . NOT(B)) + C.

Question 42Computer architecture, operating systems and networks

Consider a 4-variable Boolean function F(A, B, C, D) defined by minterms Sigma m(0, 2, 8, 10) with don't-care conditions d(5, 13). What is the minimal Sum-of-Products (SOP) expression for F?

  1. F = NOT(B) . NOT(D) Correct answer.
  2. F = NOT(A) . NOT(C)
  3. F = (NOT(B) . NOT(D)) + (B . D)
  4. F = NOT(A) . NOT(B) . NOT(D) + A . NOT(B) . NOT(D)

Explanation

Minterms 0 (0000), 2 (0010), 8 (1000), and 10 (1010) occupy the four corner cells of a 4-variable Karnaugh map. Combining these four corner cells into a single quad group eliminates variables A and C (since A varies between 0 and 1, and C varies between 0 and 1), leaving the simplified minimal product term NOT(B) . NOT(D). Don't care conditions at 5 and 13 are not needed and left as 0.

Question 43Computer architecture, operating systems and networks

How is a 1-bit binary Full Adder correctly constructed from standard combinational logic components?

  1. One Half Adder and two OR gates.
  2. Two Half Adders and one OR gate. Correct answer.
  3. Three Half Adders and one AND gate.
  4. Two Full Subtractors and one NOT gate.

Explanation

A Full Adder adds three 1-bit inputs (A, B, Cin). The first Half Adder adds A and B to produce an intermediate sum (A XOR B) and carry (A AND B). The second Half Adder adds the intermediate sum and Cin to produce the final Sum bit (A XOR B XOR Cin). An OR gate combines the carry outputs of both Half Adders to generate the final Cout.

Question 44Computer architecture, operating systems and networks

A 4-to-1 Multiplexer (MUX) has four data inputs I0, I1, I2, I3 and two select lines S1 (MSB) and S0 (LSB). Which Boolean equation represents the multiplexer output Y?

  1. Y = (NOT(S1).NOT(S0).I0) + (NOT(S1).S0.I1) + (S1.NOT(S0).I2) + (S1.S0.I3) Correct answer.
  2. Y = (S1 + S0 + I0) . (S1 + NOT(S0) + I1) . (NOT(S1) + S0 + I2) . (NOT(S1) + NOT(S0) + I3)
  3. Y = (S1.S0.I0) + (S1.NOT(S0).I1) + (NOT(S1).S0.I2) + (NOT(S1).NOT(S0).I3)
  4. Y = I0 XOR I1 XOR I2 XOR I3 XOR S1 XOR S0

Explanation

The select inputs decode the active channel: when S1S0 = 00, output Y = I0; when S1S0 = 01, Y = I1; when S1S0 = 10, Y = I2; when S1S0 = 11, Y = I3. Summing these mutually exclusive AND terms gives: Y = (NOT(S1).NOT(S0).I0) + (NOT(S1).S0.I1) + (S1.NOT(S0).I2) + (S1.S0.I3).

Question 45Computer architecture, operating systems and networks

In sequential digital logic, what happens to the output state Q of an edge-triggered JK flip-flop when both J and K inputs are held at logic HIGH (1) during an active clock transition?

  1. The output enters an illegal, indeterminate metastable state.
  2. The output remains latched in its previous state without change.
  3. The output is reset unconditionally to logic 0.
  4. The output toggles to the complement of its previous state (Q_next = NOT(Q)). Correct answer.

Explanation

Unlike the basic SR latch where S=1, R=1 produces an invalid state, the JK flip-flop resolves this condition. When J=1 and K=1, the active clock edge causes the flip-flop to toggle its output state, so Q_next = NOT(Q).

Question 46Programming and software development

Which sequence correctly depicts the chronological order of phases in the classical Software Development Life Cycle (SDLC)?

  1. Implementation (Coding) -> Testing -> Requirements Analysis -> Design -> Maintenance
  2. Feasibility Study -> Requirements Analysis -> System Design -> Implementation (Coding) -> Testing -> Deployment & Maintenance Correct answer.
  3. System Design -> Testing -> Implementation -> Feasibility Study -> Deployment
  4. Requirements Analysis -> Maintenance -> Testing -> System Design -> Implementation

Explanation

The traditional SDLC begins with determining viability (Feasibility Study), followed by gathering and specifying needs (Requirements Analysis), architecting the solution (System Design), writing code (Implementation), verifying correctness (Testing), and releasing/supporting the system (Deployment & Maintenance).

Question 47Programming and software development

What is widely recognized as the primary operational drawback of the traditional Waterfall software process model?

  1. It lacks formal documentation and sign-off criteria between phases.
  2. It is highly rigid and inflexible to changing user requirements once development has progressed past early stages. Correct answer.
  3. It requires daily client standup meetings and short 2-week iteration cycles.
  4. It cannot be used for small-scale projects with well-defined, static requirements.

Explanation

The Waterfall model is linear and sequential; each phase must be fully completed and signed off before the next begins. Because working software is delivered only at the end of the lifecycle, accommodating late requirement changes or design flaws is extremely costly and difficult.

Question 48Programming and software development

According to the Manifesto for Agile Software Development, which value is prioritized over 'comprehensive documentation'?

  1. Contract negotiation
  2. Following a rigid plan
  3. Working software Correct answer.
  4. Standardized toolchains

Explanation

The Agile Manifesto states four core value pairs: 'Individuals and interactions over processes and tools; Working software over comprehensive documentation; Customer collaboration over contract negotiation; Responding to change over following a plan.'

Question 49Programming and software development

In the Scrum agile framework, what is the primary responsibility of the Product Owner?

  1. Facilitating daily standup meetings and removing technical impediments for the development team.
  2. Managing and prioritizing the items in the Product Backlog to maximize the business value delivered by the team. Correct answer.
  3. Writing automated unit test suites and executing continuous integration builds.
  4. Designing low-level database schemas and configuring production cloud servers.

Explanation

The Product Owner is the voice of the customer and business stakeholders. They are solely responsible for creating, grooming, and prioritizing User Stories in the Product Backlog to ensure the team delivers maximum value each Sprint.

Question 50Programming and software development

What fundamental feature distinguishes Boehm's Spiral Model from other software engineering process models?

  1. The complete omission of software prototyping during early development.
  2. An explicit, structured risk analysis and risk management phase in every iterative cycle of the spiral. Correct answer.
  3. The requirement that all system coding must be finished in a single uninterrupted sprint.
  4. The replacement of testing phases with formal mathematical proofs.

Explanation

Boehm's Spiral Model is inherently risk-driven. Each radial cycle around the four quadrants (Determine objectives, Evaluate alternatives and resolve risks, Develop and test, Plan next phase) incorporates an explicit risk analysis phase to identify, mitigate, and resolve project risks before committing further resources.