Computer Hardware and Organisation: CPU, Memory, I/O and Storage
Computer hardware and organisation covers the physical machine: how the processor executes instructions, how memory holds programs and data, how buses move information, and how input, output and storage devices are chosen for a task. The exam asks for register roles, comparisons of storage media, and justified device choices in a scenario.
CPU, registers and buses
The CPU contains the arithmetic logic unit (ALU), which performs arithmetic and logical comparisons; the control unit, which decodes instructions and coordinates the components; and registers. Know the program counter (address of the next instruction), memory address register and memory data register (the two ends of a memory transfer), current instruction register and accumulator. The fetch–decode–execute cycle repeats: copy the instruction at the program counter into the CIR, decode it, execute it, store the result, increment the program counter. Performance is described by clock speed, core count and cache size; cache is small, costly SRAM close to the CPU and faster than main memory. The address bus carries locations, the data bus carries contents, the control bus carries read/write and timing signals.
Memory and storage
RAM is volatile working storage holding the operating system, programs and current data; ROM is non-volatile and holds the bootstrap/firmware. Virtual memory extends RAM onto disk by paging, but heavy use causes thrashing. Compare storage on capacity, access speed, cost per gigabyte, portability and durability: magnetic hard disks give cheap high capacity but contain moving parts; SSDs are faster, silent and shock-resistant but dearer per gigabyte; optical media suit distribution and archiving; flash suits portable devices. Input devices include keyboards, scanners, barcode readers, OMR, OCR, microphones and sensors; output includes monitors, projectors, laser/inkjet/dot-matrix printers and actuators. Choose devices by data type, volume, accuracy and environment.
Worked example
A machine has a 24-bit address bus and is byte-addressable. Each address identifies one byte, so there are 2^24 = 16,777,216 addresses, that is 16 MiB of directly addressable memory. With a 20-bit bus the figure would be 2^20 = 1,048,576 bytes = 1 MiB; each extra address line doubles the addressable space.
Traps
Do not confuse bus width with word size, or cache with main memory - cache is faster and smaller. RAM is volatile, ROM is not, though some flash-based firmware can be rewritten. Do not claim SSDs have platters or that defragmentation helps them.