Computer architecture, logic and data representation
Computer architecture and hardware
This domain examines the stored-program machine: how instructions and data share one memory, how the processor fetches and executes them, and how the memory hierarchy and instruction-set design affect performance.
The von Neumann model
Instructions and data share one memory and one set of buses. The address bus is unidirectional and its width fixes addressable memory: n lines distinguish 2ⁿ addresses in this simplified model. The addressable unit must be specified; data-bus width alone does not determine whether addresses identify bytes or words. The data bus is bidirectional and its width fixes the word moved per transfer. The control bus carries read/write, clock and interrupt signals.
Registers and the fetch–decode–execute cycle
- PC holds the address of the next instruction; MAR holds the address currently being accessed.
- MDR holds the data or instruction just read, or about to be written; CIR holds the instruction being executed.
- ACC is the accumulator; the ALU performs arithmetic and logic; the CU decodes and issues control signals.
- In a simplified precise-interrupt model, an interrupt is accepted at an architectural boundary, required state is preserved and control transfers to its handler. The exact state-save mechanism depends on the processor.
Improving performance
Pipelining overlaps fetch, decode and execute for consecutive instructions. Cache exploits temporal and spatial locality to cut average memory access time. Traditional RISC and CISC teaching models contrast simpler instruction sets with richer instructions; actual encodings, micro-operations and implementation performance vary. Neither label alone proves fewer instructions or faster execution.
Worked example
A processor has a 20-bit address bus and 16-bit data bus. How much memory can it address, and what happens when it executes LDA 300?
Addressable memory = 2²⁰ = 1,048,576 locations =2 MiB if each addressed location is a 16-bit word, or 1 MiB if addresses identify bytes. The 20-bit address count alone does not settle this choice. During fetch the PC contents go to the MAR, memory returns the instruction to the MDR and it is copied to the CIR; the PC increments. During execute, address 300 goes to the MAR, the operand is read into the MDR and loaded into the ACC. STA 302 reverses this, sending the ACC value through the MDR to address 302.
Traps that cost marks
- Saying the MAR holds the instruction; it holds an address, and the CIR holds the instruction.
- Forgetting that the PC increments during fetch, before execution.
- Confusing cache (hardware-managed, transparent) with virtual memory (disk-backed, causes page faults).
- Claiming RISC programs always execute fewer instructions.
- Misstating bus direction: address out only, data both ways.
Core concepts
Candidates must be fluent in number systems and data representation (binary, octal, hex, two's complement, BCD, ASCII/Unicode), logic gates and Boolean algebra, and the fetch-decode-execute cycle. Know the roles of the program counter, instruction register, memory address register, accumulator, and control unit. Understand the memory hierarchy (registers, cache, RAM, secondary storage) with its speed-cost-capacity trade-offs, and the distinction between RISC and CISC, von Neumann and Harvard architectures, and direct versus associative cache mapping. Be clear about bus types (address, data, control), interrupts, and pipelining hazards.
Traps
Questions often test the range of two's complement (an n-bit signed integer spans -2^(n-1) to 2^(n-1)-1), the difference between a bit and a byte, and the fact that hexadecimal is only a compact notation, not a separate machine representation. Another common trap: conflating clock speed with throughput, or assuming cache increases main memory capacity. Watch for questions that ask which register holds the address of the next instruction (PC) versus the instruction itself (IR).
Worked example
Represent -5 in 8-bit two's complement. Write +5 as 0000 0101, invert to 1111 1010, add 1 to get 1111 1011. Check: the leading 1 signals negative, and the value is -128 + 64 + 32 + 16 + 8 + 2 + 1 = -5. Rule of thumb: invert-and-add-one always yields the correct two's complement, and the same bit pattern can be read as unsigned 251, so always state the interpretation.