Battery Monitor Divider Loaded by ADC Input
An electronics technician is troubleshooting a 12 V battery monitor. The pack voltage is confirmed at 12.0 V with a calibrated bench DMM. The board uses a divider with R1 = 100 kΩ from +12 V to node A and R2 = 47 kΩ from node A to ground. Node A drives a microcontroller ADC channel whose datasheet specifies a 100 kΩ input impedance; the ADC sample capacitor is 10 pF. Firmware converts the measured node voltage using the unloaded divider ratio and displays 9.1 V, so the operator believes the pack is deeply discharged. On the bench, a 10 MΩ DMM at node A reads about 3.81 V, which looks correct. The board is battery powered and the designer wants the divider drain current kept below 100 µA. The technician must explain the discrepancy and propose a fix that does not drain the pack.
1. Calculate the voltage at node A with the ADC disconnected and connected, and explain why the firmware displays 9.1 V for a 12.0 V pack.
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Unloaded divider: V_A = 12.0 × 47k/(100k + 47k) = 12.0 × 0.3197 = 3.837 V. The ADC input is not infinite: 100 kΩ in parallel with 47 kΩ gives R2' = (47 × 100)/(147) = 31.97 kΩ. Loaded V_A = 12.0 × 31.97/(100 + 31.97) = 2.906 V. Firmware uses the unloaded ratio k = (100 + 47)/47 = 3.128, so it reports 2.906 × 3.128 = 9.09 V, matching the 9.1 V display. The 10 MΩ DMM barely loads the node: 47k || 10M = 46.78 kΩ, giving 3.82 V, so the bench reading looks correct and masks the ADC loading. The pack is actually 12.0 V; the error is measurement loading, not a battery fault.
2. Recommend two circuit fixes and compare them against the 100 µA drain budget and accuracy.
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Option A is a unity-gain buffer between node A and the ADC, using a rail-to-rail CMOS op-amp with low input bias current and low offset. The divider then sees only picoamps to nanoamps, so the unloaded equation is valid and the 12 V/147 kΩ = 82 µA drain is unchanged. Cost is one part, board space, and quiescent current that must stay small for battery life. Option B is to lower the resistors to 10 kΩ and 4.7 kΩ. The Thevenin resistance falls to about 3.2 kΩ, so a 100 kΩ ADC load causes only about 3% error, but the divider draws 12 V/14.7 kΩ = 0.82 mA, far above the 100 µA budget, so this is unacceptable here. A firmware calibration for the 100 kΩ load could work only if that impedance is tightly specified and stable over temperature, which ADCs often do not guarantee. Choose the buffer; a 47 kΩ/22 kΩ divider with calibration is a fallback but raises drain to about 174 µA.
3. Determine the Thevenin equivalent seen by the ADC and explain why source impedance matters for a 10 pF sample capacitor.
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Rth = R1 || R2 = 100k || 47k = 31.97 kΩ, and Vth = 3.837 V. The 10 pF sample capacitor gives τ = 31.97k × 10p = 0.32 µs. That seems fast, but the sample switch adds resistance and the acquisition window may be only a few microseconds. Settling to 0.5 LSB of a 12-bit converter can require several time constants, and 32 kΩ often exceeds the ADC datasheet's maximum recommended source impedance. The 100 kΩ DC input impedance also shifts the divider operating point, as the loaded calculation shows. A buffer drops the source impedance to well under 1 kΩ, making settling independent of the divider and preserving accuracy. The technician should check the ADC's specified maximum source impedance and acquisition time before trusting the 0.32 µs figure.