Computer Organization: CPU, Memory, Storage and the Operating System
Topic 2 is the machine itself: how the CPU executes instructions, how memory is addressed, how data is represented and stored, and how the operating system manages resources. Questions often ask you to follow the instruction cycle in order or to perform a short calculation, so precision matters more than breadth.
The machine instruction cycle
Fetch: the address of the next instruction is copied from the PC to the MAR, the instruction travels over the data bus into the MBR and then the IR, and the PC is incremented. Decode: the control unit interprets the opcode. Execute: the ALU performs the operation and the result goes to a register or back to memory. Buses: address bus (unidirectional, carries addresses), data bus (bidirectional, carries data and instructions), control bus (carries timing and control signals). Key registers: PC, MAR, MBR, IR, ACC.
Memory, storage and the OS
RAM is volatile primary storage; ROM holds the bootstrap; cache is small, fast and close to the CPU; virtual memory extends RAM using secondary storage, swapping pages in and out. With n address lines, 2^n locations can be addressed. Storage: magnetic (cheap per GB, moving parts), optical (durable, slow), solid state (fast, no moving parts, limited write cycles, expensive per GB). The OS handles memory management, scheduling, hardware abstraction through drivers, file management and security.
Worked example
A CPU has 20 address lines and a 16-bit word size. How much memory can it address? 2^20 = 1 048 576 locations; each is 16 bits = 2 bytes; so 2 MiB. Reasoning: address lines fix the number of locations, the word size fixes the size of each location. Multiplying the two before converting to bytes is the usual error.
Traps that cost marks
- Saying the PC holds the instruction - it holds the address of the next instruction.
- Claiming cache is larger than RAM, or that virtual memory is faster than RAM.
- Forgetting that interrupts are checked at the end of the cycle, and confusing polling with interrupts.
- Mixing up which bus is unidirectional.