Computer Systems and Architecture
Computer Systems and Architecture tests how hardware and software cooperate: the processor’s fetch–decode–execute cycle, registers, memory hierarchy, buses, and performance measurement. Expect questions that ask you to trace an instruction, compare cache and main memory, or calculate execution time.
Processor model
The CPU contains an arithmetic logic unit (ALU), control unit, and registers. The program counter (PC) holds the next instruction address; the instruction register (IR) holds the current instruction; the accumulator or general registers hold operands. In the von Neumann model, instructions and data share memory, so a single bus can create a bottleneck. Harvard-style designs separate instruction and data paths.
Memory hierarchy and buses
Registers are fastest and smallest, then cache (L1/L2/L3), main memory (RAM), and secondary storage. Cache exploits locality: temporal locality means recently used data is likely reused; spatial locality means nearby addresses are likely used. The address bus carries addresses, the data bus carries values, and the control bus carries read/write and timing signals.
Worked example
A 2 GHz processor executes 5×10^8 instructions with an average CPI of 4. Time = instruction count × CPI / clock rate = (5×10^8 × 4) / (2×10^9) = 1 second. Notice that GHz must be converted to cycles per second and CPI is cycles per instruction, not instructions per cycle.
Traps
Do not confuse clock rate with execution time; a higher clock does not always mean faster execution if CPI or instruction count is worse. Cache is not permanent storage. The PC holds an address, not the instruction itself. Read bus widths carefully: an n-bit address bus can address 2^n locations, not 2^n bytes unless each location is one byte.