Buck Converter Resets: Junction Temperature and a Shrinking Output Capacitor
A 24 V to 5 V synchronous buck converter on a 40 mm x 60 mm two-layer board supplies a 2 A load inside a sealed enclosure. The switcher runs at 500 kHz with a 22 uH inductor whose measured ripple is 0.9 A peak-to-peak. The MOSFET has R_DS(on) = 30 mOhm at 100 degC, and the board layout gives a junction-to-ambient thermal resistance of 60 K/W for that package. Measured dissipation splits as follows: MOSFET conduction 0.12 W, MOSFET switching 0.24 W, gate drive 0.06 W, inductor DCR 0.33 W. Enclosure air reaches 68 degC after 30 minutes of running. The output capacitor is a 22 uF, 6.3 V X5R ceramic; the vendor bias curve shows 8.8 uF effective at 5 V. Field units reset intermittently after about 20 minutes, and a scope shows the 5 V rail dipping in a 40 kHz burst that is absent on the bench at 25 degC. The MOSFET junction limit is 125 degC.
1. Compute the MOSFET junction temperature at 68 degC enclosure air. State whether the margin is acceptable, and show clearly which losses you put through the junction-to-ambient path and which you did not.
Read the worked answer
Partition the losses before you multiply. The 60 K/W figure is junction-to-ambient for the MOSFET package, so only the MOSFET's own dissipation flows through that path:
- MOSFET internal loss = conduction 0.12 + switching 0.24 + gate drive 0.06 = 0.42 W
- Delta T = 0.42 x 60 = 25 K
- Tj = 68 + 25 = 93 degC, margin 32 K to the 125 degC limit
The inductor's 0.33 W does not pass through the MOSFET junction; it heats the enclosure air, which is precisely why the ambient is 68 degC and not 40 degC. Multiplying the full 0.75 W by 60 K/W (giving 113 degC) is the common error here - it double-counts a loss that is already reflected in the measured ambient.
Verdict. Margin is acceptable but not generous. A sane design target is Tj <= 100 degC at maximum ambient, which leaves (100 - 68)/60 = 0.53 W of budget against 0.42 W used - about 0.11 W of headroom. That is thin once you allow for the thermal-resistance spread between boards. The thermal design is not the cause of the resets, but it should be logged as a reliability watch item, since every 10 K of extra junction temperature roughly halves wear-out life.
2. At 5 V bias the 22 uF capacitor delivers only 8.8 uF. Explain how this produces a 40 kHz burst in the field but not on a 25 degC bench, and state the corrective action and the test that would prove it.
Read the worked answer
Mechanism. In a voltage-mode buck the loop crossover scales roughly as 1/sqrt(L*C). Reducing effective C from 22 uF to 8.8 uF raises crossover by sqrt(22/8.8) = 1.58 times. If the bench crossover was around 25 kHz, in the field it lands near 40 kHz - close enough to the ESR zero placement and the sampling/phase lag to eat the phase margin. The result is a sustained limit-cycle oscillation whose peak-to-peak amplitude is large enough to dip the 5 V rail and brown out the downstream logic, producing the reset. It appears after 20 minutes because the enclosure has to heat up first: at 25 degC the part holds more capacitance (bias derating alone is not the whole story - X5R loses capacitance as temperature rises too), so the bench unit is marginally stable; by the time the air is at 68 degC, the capacitance has fallen further and the loop goes unstable.
Fix. Replace the 6.3 V part with a 16 V or 25 V X7R rated capacitor, or parallel two 10 V 22 uF parts, so that at least 15 uF remains at 5 V DC bias over the full temperature range. Re-check the compensator with the new capacitance.
Proof. Repeat the load-step and Bode measurement inside a chamber at 70 degC ambient, with the unit soaked for 30 minutes, sweeping the load 0.2 A to 2 A. A stable design shows no burst at the switching frequency and phase margin above 45 degrees.
3. The team has budget for only one change before the next build. Rank the two fixes (capacitor, thermal) and justify the order. What verification would you demand before release?
Read the worked answer
Capacitor first, unambiguously. The reported field failure is a reset, and the scope evidence ties the rail dip to a 40 kHz oscillation that correlates with the heated state. The thermal calculation shows the MOSFET at 93 degC - inside limits - so the thermal path cannot explain a functional failure at 20 minutes; it is a life-expectancy issue that would surface as field returns over months, not as resets in the first half hour. Sequencing the capacitor change first converts a non-functional unit into a functional one, so that the subsequent thermal characterisation is even meaningful.
Do not accept these substitutes: raising the current limit, adding a large bulk electrolytic without re-stabilising the loop, or slowing the soft-start. None of them restores phase margin.
Verification demanded:
- Eight-hour soak at 70 degC ambient, worst-case load stepping at 1 kHz and at 100 Hz.
- Capacitance measured on the actual vendor parts at 5 V, 25 degC and 85 degC - use the vendor curve, not the catalogue value.
- Junction temperature logged by thermocouple on the FET tab at the end of the soak.
- Ten units, not one, to cover part spread.
If the thermal headroom still looks thin after the capacitor change, a low-cost copper-pour change on the next revision is justified; a heatsink is not.