Microprocessors, Microcontrollers and Computer Fundamentals
This domain covers 8085 architecture and programming, memory and I/O interfacing, interrupts, the 8051 microcontroller, and number systems and basic computer organisation.
Core rules
- 8085: 8-bit data bus, 16-bit address bus (64 KB), multiplexed AD0–AD7 demultiplexed using ALE; a 6 MHz crystal gives a 3 MHz clock, so each T-state is 1/3 µs.
- Interrupt priority on the 8085: TRAP (non-maskable) highest, then RST 7.5, RST 6.5, RST 5.5, then INTR; INTA acknowledges INTR.
- 8051: 4 KB on-chip ROM, 128 bytes RAM, two 16-bit timers, five interrupt sources, four register banks; port 0 needs external pull-ups.
- Memory: n address lines address 2ⁿ locations, so a 4 KB × 8 chip needs 12 address lines.
Worked example
How many 2 KB × 8 EPROMs are needed for an 8 KB program memory, and how many address lines does each use? 8 KB / 2 KB = 4 chips. Each chip has 2¹¹ = 2048 locations, so it uses A0–A10; the upper lines A11 and A12 select one of the four chips through a decoder. The 8085 has 64 KB of address space, so 8 KB is used and 56 KB remains for RAM and I/O.
Traps
Computing address lines from byte count instead of word count; forgetting that AD0–AD7 carry both address and data; assuming RST 5.5 outranks RST 7.5; and miscounting the 8085 flags, which are five: S, Z, AC, P and CY.