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FET: Electrical Circuits, Power, and Electronics

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Electrical Circuits, Power, and Electronics

Circuit questions reward systematic reduction: series and parallel combinations, node equations, and source transformations. Power questions test single- and three-phase relationships along with power-factor correction.

Core rules

  • Use KVL and KCL. Series resistances add; parallel conductances add. The voltage divider gives V_x = V(R_x/R_total).
  • Thevenin equivalent: open-circuit voltage in series with the resistance seen with all sources dead. Maximum power transfer occurs at R_L = R_th.
  • RC and RL transients have τ = RC or L/R; after roughly five time constants the transient is essentially over.
  • AC impedance: Z_R = R, Z_L = jωL, Z_C = 1/(jωC). RMS values satisfy V_rms = V_peak/√2. Real power P = VI cosθ; reactive Q = VI sinθ; apparent S = VI.
  • Three-phase wye: V_line = √3 V_phase; total power P = √3 V_LL I_L cosθ.
  • Electronics: a silicon diode drops about 0.7 V; a BJT in active mode needs a forward-biased base–emitter junction and a reverse-biased collector–base junction; an ideal op-amp gives a virtual short and draws no input current.

Worked example

A 480 V line-to-line, 50 A three-phase motor at 0.85 power factor draws P = √3(480)(50)(0.85) = 35.3 kW. Apparent power is 41.6 kVA, so reactive power is √(41.6² − 35.3²) = 22.0 kvar. Adding about 22 kvar of parallel capacitance brings the factor near unity and reduces line current.

Traps

  • Using peak voltage where RMS belongs in power calculations.
  • Mixing line and phase quantities in a delta connection.
  • Placing power-factor correction capacitors in series rather than parallel.
  • Assuming an ideal op-amp model still holds once the output saturates.