Twelve-Bit SAR Front End That Settles Badly After Channel Switching
An eight-channel data-acquisition front end uses a 12-bit SAR ADC with a 5.000 V reference and a 20 MHz conversion clock; a conversion takes 13 clock cycles and the sample-and-hold acquisition window is fixed at 250 ns. Each channel is a piezoelectric accelerometer followed by a charge amplifier whose output resistance is 10 kΩ, then a 400 Ω multiplexer switch and the ADC's 15 pF sampling capacitor. Full scale is ±5 V and the design target is ±0.5 LSB at the ADC input. On the prototype, a steady 2.500 V on one channel reads correctly when that channel is selected repeatedly, but the first conversion after switching from a channel sitting at 0 V reads about 0.4 V low. Firmware scans all eight channels back-to-back at the full 1 MSPS aggregate rate. The accelerometer signals of interest are below 10 kHz, and all eight channels must be recorded simultaneously for at least 20 minutes without gaps.
1. Compute the settling error and derive the maximum source resistance the ADC can tolerate in a 250 ns acquisition window.
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Acquisition is a first-order settling problem with τ = (R_source + R_mux) × C = (10 kΩ + 0.4 kΩ) × 15 pF = 156 ns. The 250 ns window is 250/156 = 1.6 τ, leaving e^(−1.6) = 20 % of the step unsettled; for a full 5 V step that is about 1.0 V, and with charge injection and the actual channel step the observed 0.4 V is consistent. The target of 0.5 LSB is 5 V/8192 = 0.61 mV, so the permitted residue as a fraction of a full step is 0.61 mV/5 V = 1.22 × 10⁻⁴, requiring ln(1/1.22 × 10⁻⁴) = 9.0 τ. With 250 ns available, τ must be at most 250/9.0 = 27.8 ns, so total series resistance must be at most 27.8 ns / 15 pF = 1.85 kΩ. The 10.4 kΩ presently in series is about 5.6 times too high. Two conclusions follow: the ADC is not faulty, and any fix must either lower source impedance or lengthen acquisition.
2. Choose between adding unity-gain buffers and extending the acquisition window. Justify with throughput numbers.
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Conversion is 13 clocks at 20 MHz, i.e. 650 ns. At present each channel slot is 650 + 250 = 900 ns, giving 1.11 MSPS aggregate and 139 kSPS per channel. Extending acquisition to 1.4 µs, which is 9τ for the existing 10.4 kΩ source, makes each slot 2.05 µs: 488 kSPS aggregate and 61 kSPS per channel. For signals below 10 kHz that is three times Nyquist, so it is adequate, and 20 minutes of eight-channel recording at 2 bytes per sample is about 1.2 GB, which is manageable. The buffer alternative needs eight op-amps, adds its own settling, offset and noise, and costs board area and power. Since the bandwidth requirement is modest, the firmware change is the better first move: it costs nothing and preserves accuracy. Add buffers only if a channel later needs more than about 30 kSPS, and in either case fit an anti-alias filter ahead of the multiplexer, because 61 kSPS sampling of a 10 kHz signal leaves little margin against out-of-band noise.
3. What else in the front end could corrupt the reading even after settling is fixed?
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Settling is necessary but not sufficient. Charge injection from the multiplexer and the ADC's sampling switch appears as a step at every channel change and is worst on the first sample after switching, so the first conversion of each slot should be discarded if throughput allows. Off-channel leakage and the multiplexer's finite off-isolation allow a large signal on an adjacent channel to bleed into the selected one. The 12-bit, 0.5 LSB target also implies roughly 70 dB of noise-free dynamic range, which a 5 V reference SAR rarely achieves without careful layout, a clean ground plane and a low-impedance reference bypass; relaxing to 1 LSB is often the pragmatic choice. Finally, the charge amplifier's output resistance is specified at DC - check its output impedance over frequency, because a capacitive load at the multiplexer input can make it ring, turning a settling problem into an oscillation that no acquisition time will cure.