Technology: Digital Conversion, Sampling and Embedded Data Acquisition
GATE IN tests the digital and embedded layer of instrumentation: number systems, Boolean algebra, sequential logic, ADC/DAC conversion, sampling, microprocessors, and communication links. Questions are quantitative-code values, conversion time, aliasing frequency, quantization noise and bit-error rate.
Core rules
- An n-bit converter has 2^n output levels. For a unipolar 0 to V_FS range, LSB = V_FS/2^n (some texts use 2^n − 1 for an ideal DAC; note which convention the question uses).
- Quantization error is ±0.5 LSB for round-to-nearest. Ideal full-scale sine SNR ≈ 6.02n + 1.76 dB.
- Nyquist criterion: f_s > 2f_max. A component above f_s/2 folds to |f − k f_s|; this is aliasing, not attenuation.
- Sample-and-hold aperture uncertainty limits high-frequency accuracy: ΔV ≈ (dV/dt) × t_aperture.
- Two's complement n-bit range is −2^(n−1) to 2^(n−1) − 1; overflow wraps unless saturated.
- 4–20 mA uses 4 mA as live zero and 20 mA as full scale; the transmitter needs enough compliance voltage to drive the loop load.
Worked example
A 12-bit ADC has a 0–5 V unipolar range. There are 4096 levels, so LSB = 5/4096 = 1.221 mV. For Vin = 2.500 V, code = round(2.500/0.001221) = 2048. Quantization error is ±0.610 mV, which is 0.0122% of full scale. If the same converter is clocked at 1 µs per conversion, the maximum full-scale conversion rate is 1 MS/s, but input bandwidth is set by the sample-and-hold, not by that clock alone.
Traps that cost marks
- Mixing 2^n and 2^n − 1 when computing LSB or full-scale code.
- Forgetting the bipolar offset: a ±5 V range has 10 V span, not 5 V.
- Treating Nyquist rate as equal to signal bandwidth rather than twice it.
- Assuming a 4–20 mA transmitter can drive any load without checking compliance voltage.