Architecture: Loop Structure, PLC Scan and Automation Layers
GATE IN tests how measurement and control systems are structured: the signal chain, open versus closed loop, PLC scan behaviour, DCS/SCADA hierarchy, and final control elements. Architecture questions ask where delay, gain and failure propagate.
Core rules
- Signal chain: sensor → signal conditioning → ADC → controller → DAC → actuator. Each block contributes gain, offset and noise; errors at the input cannot be removed downstream.
- Feedback reduces sensitivity of the closed-loop gain to forward-path variations by the factor 1/(1 + GH).
- PLC scan cycle: input scan → program execution → output update. A pulse shorter than the scan time can fall between input scans and be missed.
- Worst-case input-to-output latency is roughly two scan periods; output update adds one program-plus-output delay.
- Automation hierarchy: field instruments, control level (PLC/DCS), supervisory SCADA, MES, ERP. 4–20 mA carries one variable; fieldbus carries multiple values and diagnostics.
- Control valves: fail-safe action, actuator sizing against shut-off pressure, dead band and stiction.
Worked example
A PLC has 10 ms input scan, 15 ms program execution and 5 ms output update, giving a 30 ms scan. A 10 ms pulse arriving just after the input scan is not seen; it is missed entirely. For reliable capture, the pulse width should exceed the input scan time. A pulse train faster than about 1/(2 × 30 ms) ≈ 16.7 Hz cannot be resolved reliably, by the same Nyquist argument used for sampled signals. If the event must be captured, use a latch or interrupt input rather than relying on the normal scan.
Traps that cost marks
- Ignoring output update delay and quoting only program execution time.
- Assuming a faster processor alone fixes missed pulses; the input scan and latch architecture matter.
- Treating DCS and PLC as interchangeable when the question is about redundancy or loop ownership.
- Forgetting the fail-safe position when specifying a control valve.