Digital Logic and Computer Organization
Digital logic and computer organization covers Boolean minimization, combinational and sequential circuits, number representation, CPU datapath and control, instruction formats, addressing modes, pipelining, memory hierarchy, cache, I/O, and basic floating-point arithmetic. Questions often combine a small calculation with a structural idea.
Core rules and concepts
- Use K-maps for up to five variables; group 1s in powers of two, overlap groups to cover all 1s, and use don’t-cares only when they enlarge a group.
- A flip-flop stores one bit; edge-triggered devices sample inputs at clock edges, so setup and hold times constrain reliable operation.
- In an n-bit two’s-complement system, values run from −2^(n−1) to 2^(n−1)−1; overflow occurs when adding two same-sign numbers yields the opposite sign.
- Pipelining increases throughput, not the latency of one instruction; speedup is limited by the slowest stage and pipeline stalls.
- Cache address bits split into tag, index, and offset. The offset width is log2(block size); the index width is log2(number of sets); the tag is the remainder.
Worked example
A 32-bit byte-addressed machine has a 64 KB four-way set-associative cache with 64-byte blocks. Number of lines = 64 KB / 64 B = 1024. Number of sets = 1024 / 4 = 256, so index bits = log2(256)=8. Offset bits = log2(64)=6. Tag bits = 32−8−6=18. Thus each address is interpreted as 18 tag bits, 8 index bits, and 6 offset bits.
Traps that cost marks
Using total cache size instead of number of sets for index bits; forgetting that associativity reduces set count; confusing throughput with latency; and assuming a larger cache always improves hit time. In sequential circuits, do not ignore the initial state or asynchronous clear.