Programmable Logic Controllers and Control Systems
Programmable Logic Controllers and Control Systems
This domain tests PLC operation, ladder logic, timers and counters, analogue scaling, interlocks and the difference between open and closed-loop control. Expect a ladder rung to interpret or a scaling and timing calculation.
Core rules
- Scan cycle: read inputs into the image table, solve the program from top to bottom and left to right, then update outputs. Outputs therefore respond one scan late, and a coil written twice in a program is resolved by the last rung.
- Ladder: examine-if-closed (normally open) passes power when the bit is 1; examine-if-open passes when the bit is 0; a latch uses its own contact in parallel with the start condition; an interlock prevents conflicting outputs.
- Timers: TON delays on, TOF delays off, RTO retains time and needs a reset. Preset counts = time / time base, so 5 s at 100 ms = 50 counts. Counters increment on rising edges.
- Analogue scaling: engineering value = lower range + (raw − raw minimum) × span / (raw maximum − raw minimum).
- Closed loop uses feedback and a controller (P, I, D); open loop has no feedback. PID: proportional reacts to error, integral removes offset, derivative damps rate of change.
Worked example
A 4–20 mA signal from a 0–150 °C transmitter feeds a 12-bit input (0 counts at 4 mA, 4095 at 20 mA). At 12 mA the fraction is (12 − 4)/16 = 0.5, raw ≈ 2048, and temperature = 0 + 2048 × 150/4095 ≈ 75 °C. For a 5 s on-delay with a 100 ms base, set the preset to 50.
Traps
Assuming outputs change instantly in the same scan; using a double coil; forgetting to reset an RTO; scaling from 0 mA instead of 4 mA; treating a normally closed field contact as a normally closed instruction.