Mirrored Addresses on an 8085 Project Board
A polytechnic final-year project uses an 8085 CPU with a 16-bit address bus (A0–A15). The board carries one 8K×8 EPROM, one 8K×8 RAM, and a 2K×8 memory-mapped display buffer. The intended map is EPROM 0000H–1FFFH, RAM 4000H–5FFFH, and display 8000H–87FFH. During testing, writing 55H to 4100H also changes the byte at 4500H, and the display responds at both 8000H and 8800H. The RAM is soldered directly, so only decoder and chip-select wiring can be altered. A 74LS138 decoder with active-low outputs and a 74LS32 OR gate are available. The CPU's IO/M line is high for memory accesses. The lab wants no mirrored addresses and at least 8 KB of unused address space reserved for a future RAM chip. The EPROM, RAM, and display chips themselves are fixed and cannot be replaced.
1. Determine how many address lines each chip needs, and diagnose the two mirroring symptoms from the addresses given. Show the binary address ranges you use.
Read the worked answer
An 8K chip needs 13 address lines (2^13 = 8K), so A0–A12. A 2K chip needs 11 lines (2^11 = 2K), so A0–A10.
RAM symptom: 4100H and 4500H differ by 0400H, which is bit A10. Both addresses lie inside the intended 8K RAM block 4000H–5FFFH, so A10 is part of the address the RAM should decode. If changing A10 does not select a different location, A10 is effectively not reaching the RAM chip. The 8K RAM is behaving like smaller mirrored blocks.
Display symptom: 8000H and 8800H differ by 0800H, which is A11. The display needs only A0–A10. To place it at 8000H–87FFH, A11 and A12 must both be 0. If the decoder selects the whole 8K region 8000H–9FFFH, the 2K display appears four times: 8000H, 8800H, 9000H, and 9800H. The decoder is therefore ignoring A11 (and A12).
2. Propose a corrected 74LS138 decoding scheme. State which address lines drive the select inputs, which outputs select the EPROM, RAM, and display, and how the display is restricted to 2 KB without overlapping another block.
Read the worked answer
Use A15, A14, and A13 as the 74LS138 select inputs C, B, and A. Each output then covers an 8K block:
| Output | Block | Use |
|---|---|---|
| Y0 | 0000H–1FFFH | EPROM |
| Y1 | 2000H–3FFFH | free 8K |
| Y2 | 4000H–5FFFH | RAM |
| Y3 | 6000H–7FFFH | free |
| Y4 | 8000H–9FFFH | display region |
| Y5–Y7 | A000H–FFFFH | free |
The EPROM chip select is Y0, and the RAM chip select is Y2. Y4 alone would select 8K, so the display needs extra qualification. Use the OR gate to combine Y4, A11, and A12: display CS = Y4 OR A11 OR A12. Because CS is active-low, it goes low only when Y4 is low and both A11 and A12 are 0. That restricts the display to 8000H–87FFH. The region 8800H–9FFFH becomes unused, and the 8K at 2000H–3FFFH remains available for the future RAM chip.
3. Explain why connecting the 2K display directly to Y4 would create exactly four images, and why the OR-gate solution removes all of them.
Read the worked answer
Y4 covers the 8K range 8000H–9FFFH. An 8K range contains four non-overlapping 2K pages because 8K ÷ 2K = 4. The pages start at 8000H, 8800H, 9000H, and 9800H; they are distinguished by A11 and A12.
If the display's CS is tied directly to Y4, the display is selected for all four pages, so the same 2K of display memory appears at four addresses. That is address mirroring, not four separate devices.
The OR gate makes CS high-and therefore inactive-whenever A11 or A12 is 1. Only when Y4 is active and A11 = A12 = 0 does CS go low. This leaves one valid 2K window at 8000H–87FFH and makes the other three pages inaccessible to the display, so no mirror remains.