Computer Organization and Architecture
Computer Organization and Architecture tests the stored-program model, CPU components, registers, buses, the memory hierarchy and the instruction cycle.
Core rules
- The von Neumann model stores program instructions and data in the same memory; the CPU fetches, decodes and executes instructions one by one.
- The CPU contains the ALU for arithmetic and logic, the control unit for sequencing, and registers for temporary storage.
- Key registers: PC holds the next instruction address, IR holds the current instruction, MAR holds a memory address, MDR holds transferred data, and the accumulator holds intermediate results.
- The address bus carries addresses from the CPU; the data bus carries data both ways; the control bus carries read/write and timing signals.
- An n-bit address bus can select 2^n memory locations.
- Memory hierarchy from fastest to slowest: registers, cache, main memory (RAM), secondary storage. RAM is volatile; ROM is non-volatile.
- The instruction cycle is fetch, decode, execute, then store results if needed.
Worked example
A system has a 16-bit address bus and an 8-bit data bus, with one byte per location. The number of addresses is 2^16 = 65,536 = 64K. Since each address holds 8 bits (1 byte), the directly addressable memory is 64K × 1 byte = 64 KB. Doubling the address bus to 17 bits would double the address space to 128K locations.
Traps that cost marks
- Swapping the roles of the address bus and data bus.
- Saying RAM keeps its contents when power is off; only ROM and secondary storage do.
- Claiming cache is larger than main memory; it is smaller but faster.
- Confusing 1 KB (1024 bytes) with 1000 bytes in memory-size calculations.
- Forgetting that the PC holds an address, not the instruction itself.