CE Amplifier Gain, Bypass Capacitor and Clipping
A trainee builds a single-stage common-emitter preamplifier with a BC547B. The design brief requires a stable voltage gain of about 5 and an output that can drive a 10 kΩ load without clipping. Values are Vcc = 9 V, R1 = 47 kΩ, R2 = 10 kΩ, Rc = 2.2 kΩ, Re = 470 Ω, input and output coupling capacitors 10 µF, and no emitter bypass capacitor. The trainee secretly fits a 100 µF capacitor across Re because it gives more gain. With a 1 kHz, 100 mV peak-to-peak input, the output is 7.2 V peak-to-peak but the positive and negative peaks are flattened. DC measurements are Vb = 1.6 V, Ve = 0.9 V and Vc = 4.9 V. The signal generator has a 600 Ω output impedance. The trainee has a 100 µF/16 V capacitor and a 10 µF/16 V capacitor in the parts box.
1. Calculate the gain with and without the 100 µF bypass at 1 kHz. Which build explains the measured output?
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First find the emitter current: Ie ≈ Ve/Re = 0.9/470 = 1.91 mA. The intrinsic emitter resistance is re = 26 mV/Ie = 26 mV/1.91 mA ≈ 13.6 Ω. Without bypass, and with the 10 kΩ load, Rc||RL = 2.2k||10k = 1.80 kΩ. Av ≈ (Rc||RL)/(Re + re) = 1800/(470 + 13.6) ≈ 3.7. With the 100 µF bypass at 1 kHz, Xc = 1/(2π×1000×100×10^-6) ≈ 1.59 Ω. Av ≈ 1800/(1.59 + 13.6) ≈ 118. The measured 7.2 Vpp/100 mV = 72 is a clipped value, so the small-signal gain cannot be read directly; the high gain and clipping show that the bypass capacitor is fitted. The build does not match the brief.
2. Explain the flattened peaks and decide whether removing the bypass capacitor is the right fix. Include the available swing.
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The dc operating point gives Vc = 4.9 V, Ve = 0.9 V, so VCE ≈ 4.0 V. The collector can swing up to about 9 V, i.e. +4.1 V, and down to about 1.1 V before saturation, i.e. -3.8 V. The maximum undistorted output is therefore only about 7.5-8 Vpp. With a gain near 118 and a 100 mVpp input, the demanded output is about 11.8 Vpp, which exceeds the available swing, so the peaks flatten. Removing the 100 µF bypass lowers the gain to about 3.7 with the 10 kΩ load, giving about 0.37 Vpp output; that is well inside the swing and meets the stability aim, though it is slightly below the target gain of 5. So removal is the correct first fix, followed by a small design adjustment if gain 5 is essential.
3. Suggest a design change that gives gain ≈5 with the 10 kΩ load, and check that it will not clip.
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Keep the same dc bias and remove the bypass. For Av = 5, the denominator must be (Rc||RL)/5. With Rc = 2.2 kΩ and RL = 10 kΩ, Rc||RL = 1.80 kΩ, so Re + re = 360 Ω. Since re ≈ 13.6 Ω, choose Re ≈ 330-360 Ω. A 330 Ω emitter resistor gives Av ≈ 1800/(330 + 13.6) ≈ 5.2. The bias current will rise somewhat because Ve is set by the base divider; check that Vc stays high enough. With the original bias, Ie would be about 0.9/330 = 2.7 mA, Vc = 9 - 2.7m×2.2k ≈ 3.0 V, leaving roughly 3 V positive swing and 2 V negative swing, about 4 Vpp. A 100 mV input at gain 5 needs 0.5 Vpp, so there is ample margin. Alternatively, keep Re = 470 Ω and increase Rc to about 3.3 kΩ, but check the lower Vc. In either case, verify with a scope and a 1 kHz square wave.