Loaded Voltage Divider for a Data Logger
An engineer is connecting a 12.00 V reference supply across a two-resistor divider to scale a signal for a data logger. R1 = 1.00 MΩ from +12 V to the output node; R2 = 2.20 MΩ from the output node to ground. With a handheld DMM whose input resistance is 10.0 MΩ across R2, the reading is 7.72 V instead of the expected 8.25 V. Both resistors are 1% metal-film types, and the supply is within 0.05%. The logger analog input is specified as 10 MΩ to ground and accepts 0–10 V. The engineer needs an output between 8.0 V and 8.4 V at the logger input and wonders whether replacing R2 with a 2.40 MΩ resistor will fix the reading or merely shift the error. The board has a spare rail-to-rail op-amp that can be configured as a unity-gain buffer.
1. Show that the 7.72 V reading is consistent with meter loading, and rule out resistor tolerance as the main cause.
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With no meter connected, the ideal output is 12.00 × 2.20/(1.00 + 2.20) = 8.25 V. The DMM does not have infinite resistance. Its 10.0 MΩ input appears in parallel with R2: Rp = (2.20 × 10.0)/(2.20 + 10.0) = 1.803 MΩ. The loaded output is then 12.00 × 1.803/(1.00 + 1.803) = 7.72 V, exactly the observed reading.
Resistor tolerance cannot explain this. With 1% resistors, the unloaded output could range from about 12.00 × 2.178/(1.01 + 2.178) = 8.20 V to 12.00 × 2.222/(0.99 + 2.222) = 8.30 V. The measured 7.72 V is far outside that band. The supply tolerance is also far too small. The dominant effect is the 10 MΩ meter loading the high-resistance divider.
2. Evaluate the proposed fix of changing R2 to 2.40 MΩ with the logger's 10 MΩ input. Will it meet the 8.0–8.4 V requirement? What is the Thevenin resistance?
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With R2 = 2.40 MΩ and no load, the divider would give 12.00 × 2.40/(1.00 + 2.40) = 8.47 V. But the 10 MΩ logger input still loads the node. The new parallel resistance is Rp = (2.40 × 10.0)/(2.40 + 10.0) = 1.935 MΩ, so the actual output is 12.00 × 1.935/(1.00 + 1.935) = 7.91 V. That is below the required 8.0 V minimum, so the proposed replacement fails.
The Thevenin resistance seen by the load is R1 || R2. For the new values, Rth = (1.00 × 2.40)/(1.00 + 2.40) = 0.706 MΩ. For the original values it is 0.688 MΩ. Either way, the source resistance is comparable to a few tenths of the 10 MΩ load, so loading causes a several-percent error. Changing R2 merely shifts the unloaded voltage; it does not remove the loading problem.
3. Recommend a circuit change and a verification step. Include what output the logger will actually see.
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The clean fix is to keep the original 1.00 MΩ and 2.20 MΩ divider and add a unity-gain buffer between the divider node and the logger. The op-amp input should have resistance much greater than 0.688 MΩ, ideally at least tens of megohms; a CMOS rail-to-rail part easily meets that. The buffer then drives the 10 MΩ logger input from a low output impedance, so the divider is essentially unloaded and the logger sees about 8.25 V, comfortably inside 8.0–8.4 V.
A second acceptable fix is to scale both resistors down by a factor of ten, for example 100 kΩ and 220 kΩ. The unloaded output is still 8.25 V, but the Thevenin resistance falls to 68.8 kΩ. With the 10 MΩ logger input the output becomes about 8.19 V, still within specification. This costs more quiescent current but avoids an active component.
Verification should be done with the logger connected, not with the DMM alone, and preferably with a high-impedance meter at the logger input. Check the output at the minimum and maximum supply voltage, and confirm that the op-amp input bias current does not shift the high-resistance divider.