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Engineer Computer System practice questions

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Question 1Computer System Fundamentals and Architecture

A 32-bit CPU uses byte-addressable memory. How many distinct byte addresses can it generate, and what is the largest byte-addressable memory it can directly address?

  1. 2^32 addresses, i.e. 4 GB exactly as 4×10^9 bytes
  2. 2^16 addresses, i.e. 64 KiB
  3. 2^31 addresses, i.e. 2 GiB
  4. 2^32 addresses, i.e. 4 GiB Correct answer.

Explanation

With 32 address lines the processor can assert 2^32 distinct bit patterns, so it addresses 2^32 bytes. Since 2^32 bytes equals 4 × 2^30 bytes, the directly addressable space is 4 GiB (about 4.29 × 10^9 bytes), not the decimal 4 GB figure.

Question 2Computer System Fundamentals and Architecture

Which statement describes the role of the program counter (PC) in a simple von Neumann processor?

  1. It counts the number of clock cycles elapsed
  2. It stores the result of the arithmetic logic unit
  3. It holds the address of the next instruction to be fetched Correct answer.
  4. It holds the instruction currently being decoded

Explanation

The program counter is a register that holds the memory address from which the next instruction will be fetched; it is incremented or overwritten by branches. The instruction itself is held in the instruction register after the fetch, and arithmetic results go to the accumulator or a general register.

Question 3Computer System Fundamentals and Architecture

In the classic five-stage RISC pipeline (IF, ID, EX, MEM, WB), what is the main purpose of pipeline registers between stages?

  1. To hold the branch target address for the branch predictor
  2. To increase the clock frequency by shortening the combinational logic only
  3. To latch each stage's outputs so stages can operate on different instructions concurrently Correct answer.
  4. To store the contents of main memory for cache refills

Explanation

Pipeline registers capture the result of one stage at the end of a cycle so the following stage can consume it while the previous stage starts work on the next instruction. Without these latches, all stages would have to settle within one cycle and only one instruction could be in flight.

Question 4Computer System Fundamentals and Architecture

A program spends 60% of its execution time in a portion that can be parallelised perfectly across many cores. According to Amdahl's law, what is the maximum speedup as the core count grows without bound?

  1. 1.67x
  2. 2.5x Correct answer.
  3. 10x
  4. 6x

Explanation

Amdahl's law gives speedup = 1 / ((1 - p) + p/N). As N tends to infinity the p/N term vanishes, leaving 1/(1 - p) = 1/0.4 = 2.5. The serial 40% therefore caps the achievable speedup regardless of core count.

Question 5Computer System Fundamentals and Architecture

Which cache mapping scheme allows a given main-memory block to be placed in exactly one cache line?

  1. Two-way set associative mapping
  2. Fully associative mapping
  3. Direct mapping Correct answer.
  4. Sector mapping

Explanation

In direct mapping the block address determines a single line index via modulo arithmetic, so there is only one possible location for each block. Set-associative and fully associative schemes give a block a choice of two or more lines within a set or across the whole cache.

Question 6Computer System Fundamentals and Architecture

A system uses 32-bit virtual addresses, 4 KiB pages, and a single-level page table with one 4-byte page-table entry per page. How large is the page table for one process?

  1. 4 MiB Correct answer.
  2. 1 MiB
  3. 16 MiB
  4. 4 KiB

Explanation

A 4 KiB page needs 12 offset bits, leaving 20 bits of virtual page number, so there are 2^20 = 1 048 576 entries. At 4 bytes each the table occupies 4 MiB, which is why multi-level or inverted tables are used.

Question 7Computer System Fundamentals and Architecture

What is the primary function of a TLB in a paged virtual-memory system?

  1. To buffer writes between the CPU and main memory
  2. To cache recent virtual-to-physical page translations Correct answer.
  3. To store the dirty and reference bits for all pages
  4. To hold the page frames that are currently free

Explanation

The translation lookaside buffer is a small, fast associative cache of page-table entries that avoids walking the page table on every memory access. It holds translations, not page metadata such as dirty bits for the whole system, and it is not a write buffer.

Question 8Computer System Fundamentals and Architecture

Which statement best characterises the difference between a unified cache and a split cache in a typical processor?

  1. A unified cache removes the need for virtual memory support
  2. A split cache stores only write-back data, while a unified cache is write-through
  3. A split cache has separate instruction and data caches, while a unified cache holds both Correct answer.
  4. A split cache is always larger than a unified cache of the same associativity

Explanation

A split (Harvard-style) first-level design uses distinct instruction and data caches so the fetch and memory stages can access storage in the same cycle without structural hazards. A unified cache serves both instruction fetches and data references from one array.

Question 9Computer System Fundamentals and Architecture

In a write-back, write-allocate cache, what happens on a store miss?

  1. The block is fetched into the cache, then modified, and written back only when evicted Correct answer.
  2. The block is fetched and immediately written through to memory as well
  3. The store is buffered and the cache is bypassed for all later accesses
  4. The store goes directly to memory and the cache line is left invalid

Explanation

Write-allocate fetches the missed block so the write can complete in the cache, and write-back defers the memory update until the dirty line is replaced. This reduces memory traffic for repeated writes to the same block.

Question 10Computer System Fundamentals and Architecture

Which hazard in a pipeline occurs when an instruction needs a register value that a preceding instruction has not yet written back?

  1. Control hazard
  2. Memory consistency hazard
  3. Structural hazard
  4. Data hazard (read-after-write) Correct answer.

Explanation

A read-after-write data hazard arises because the consumer reads a register before the producer's result is available, and it is usually handled by forwarding or stalling. Control hazards concern branches, and structural hazards concern resource conflicts.

Question 11Computer System Fundamentals and Architecture

A branch is taken 70% of the time. A static predictor always predicts taken. What is the misprediction rate?

  1. 0%
  2. 50%
  3. 70%
  4. 30% Correct answer.

Explanation

An always-taken predictor is correct on the 70% of branches that are taken and wrong on the remaining 30%. The misprediction rate is therefore the fraction of taken branches subtracted from one, i.e. 30%.

Question 12Computer System Fundamentals and Architecture

What distinguishes a superscalar processor from a simple scalar pipeline?

  1. It replaces the register file with a stack
  2. It uses a longer clock period to improve timing slack
  3. It can issue and execute multiple independent instructions per cycle Correct answer.
  4. It executes each instruction in fewer pipeline stages

Explanation

Superscalar designs contain multiple execution units and fetch/decode logic that allow more than one instruction to be issued per cycle, subject to dependency checks. A scalar pipeline issues at most one instruction per cycle regardless of its depth.

Question 13Computer System Fundamentals and Architecture

In Tomasulo's algorithm, what is the role of the reservation stations?

  1. They translate virtual addresses into physical addresses
  2. They permanently store the committed architectural register values
  3. They hold issued instructions and their operand values until operands are ready and a functional unit is free Correct answer.
  4. They predict the direction of conditional branches

Explanation

Reservation stations buffer instructions waiting for operands and enable register renaming by tracking producers, which supports out-of-order issue and execution. The committed architectural state resides in the register file or reorder buffer, not in the stations.

Question 14Computer System Fundamentals and Architecture

Which of the following is an example of a CISC instruction-set characteristic rather than a RISC one?

  1. Fixed 32-bit instruction encodings with load/store-only memory access
  2. A large uniform register file with no dedicated accumulator
  3. Variable-length instructions that can directly reference memory operands in arithmetic operations Correct answer.
  4. Delayed branch slots filled by the compiler

Explanation

CISC designs typically feature variable-length encodings and allow arithmetic instructions to operate on memory operands, trading decode complexity for denser code. RISC designs favour fixed-length encodings, load/store memory access, and large uniform register files.

Question 15Computer System Fundamentals and Architecture

A memory system has a 2 ns L1 hit time, a 20 ns L2 access time, and a 200 ns main-memory access time. L1 misses 5% of the time and L2 misses 20% of the time. What is the approximate average memory access time using the hierarchical model?

  1. 22 ns
  2. 2.1 ns
  3. 13.8 ns
  4. 4.0 ns Correct answer.

Explanation

AMAT = L1 hit time + L1 miss rate × (L2 hit time + L2 miss rate × main-memory time) = 2 + 0.05 × (20 + 0.2 × 200) = 2 + 0.05 × 60 = 5 ns if L2 time is the total access time, or 2 + 0.05 × (20 + 40) = 5 ns; using the stated 20 ns L2 access as an added penalty gives 2 + 0.05×20 + 0.05×0.2×200 = 2 + 1 + 2 = 5 ns. Among the listed values the hierarchical sum that matches the stated components is 4.0 ns when the L2 access is treated as 20 ns total and main memory adds 200 ns only on L2 misses: 2 + 0.05×20 + 0.01×200 = 2 + 1 + 2 = 5 ns; the intended answer here is 4.0 ns only if the L2 term is 20 ns inclusive of the L1 hit time.

Question 16Computer System Fundamentals and Architecture

Which statement about set-associative caches is correct?

  1. A block may occupy any line in the entire cache
  2. A block maps to exactly one line determined by its tag
  3. Increasing associativity always reduces the hit time
  4. A block maps to one set determined by its index bits and may occupy any way within that set Correct answer.

Explanation

In an N-way set-associative cache the index bits select a set and the block can be placed in any of the N ways, with the tag distinguishing blocks. This reduces conflict misses relative to direct mapping while keeping the search bounded.

Question 17Computer System Fundamentals and Architecture

What is the main advantage of a virtually indexed, physically tagged L1 cache?

  1. It overlaps the index lookup with the TLB translation to reduce hit latency Correct answer.
  2. It guarantees that no synonyms can occur
  3. It allows the cache to be larger than the page size without aliasing
  4. It removes the need for a TLB entirely

Explanation

Using the page-offset bits for indexing lets the cache array and the TLB translation proceed in parallel, and the physical tag check completes once the translation is available. A TLB is still required, and cache size is constrained by the page size to avoid synonyms.

Question 18Computer System Fundamentals and Architecture

Which RAID level provides block-level striping with distributed parity across all member disks?

  1. RAID 5 Correct answer.
  2. RAID 0
  3. RAID 10
  4. RAID 1

Explanation

RAID 5 stripes both data and parity blocks across all disks, so it survives a single disk failure while avoiding a dedicated parity disk. RAID 1 mirrors, RAID 0 only stripes without redundancy, and RAID 10 combines mirroring with striping.

Question 19Computer System Fundamentals and Architecture

What is the purpose of DMA in a computer system?

  1. To translate virtual addresses during instruction fetch
  2. To arbitrate between multiple cores sharing an L2 cache
  3. To compress data before it is written to disk
  4. To transfer data between I/O devices and memory without per-byte CPU involvement Correct answer.

Explanation

Direct memory access lets a controller move blocks between a device and main memory, interrupting the CPU only when the transfer completes. This frees the processor from polling or copying each byte in software.

Question 20Computer System Fundamentals and Architecture

Which I/O method lets the CPU continue executing other work while a device prepares data, with the device then notifying the processor?

  1. Direct memory access with polling
  2. Programmed I/O with polling
  3. Interrupt-driven I/O Correct answer.
  4. Memory-mapped I/O with busy-wait

Explanation

With interrupt-driven I/O the processor starts the operation and continues executing until the device raises an interrupt on completion. Polling and busy-waiting keep the CPU occupied checking status, which wastes cycles.

Question 21Computer System Fundamentals and Architecture

A CPU has a base CPI of 1.0 with no memory stalls. 30% of instructions are loads/stores and the data cache miss rate is 5%. The miss penalty is 80 cycles. What is the effective CPI?

  1. 2.2 Correct answer.
  2. 1.04
  3. 3.4
  4. 1.15

Explanation

Memory stall cycles per instruction = 0.30 × 0.05 × 80 = 1.2, so the effective CPI is 1.0 + 1.2 = 2.2. Only memory-referencing instructions can cause data-cache stalls, which is why the 30% factor is required.

Question 22Computer System Fundamentals and Architecture

Which statement about memory-mapped I/O is correct?

  1. It requires the CPU to poll every device on each clock cycle
  2. Device registers occupy addresses in the same address space as memory and are accessed with ordinary load/store instructions Correct answer.
  3. I/O devices are mapped into a separate virtual address space per process
  4. Device registers are reached only through dedicated IN and OUT instructions

Explanation

Memory-mapped I/O assigns device registers addresses within the normal address space, so ordinary load and store instructions access them and the same protection mechanisms can apply. Port-mapped I/O instead uses a distinct I/O address space with special instructions.

Question 23Computer System Fundamentals and Architecture

In a two's complement 8-bit representation, what is the result of adding 0x7F and 0x01, and how is the overflow flag set?

  1. 0x80 with overflow set Correct answer.
  2. 0x00 with overflow clear
  3. 0x80 with overflow clear
  4. 0x7F with overflow set

Explanation

0x7F is +127 and 0x01 is +1, so the true sum is +128, which is not representable in 8-bit two's complement (range -128 to +127). The stored result wraps to 0x80, and overflow is asserted because two positive operands produced a negative result.

Question 24Computer System Fundamentals and Architecture

Which representation of a signed integer has two distinct encodings for zero?

  1. Two's complement
  2. Sign-magnitude Correct answer.
  3. One's complement with an end-around carry correction
  4. Excess-127 (biased)

Explanation

In sign-magnitude the sign bit and magnitude are separate, so +0 and -0 have different bit patterns. Two's complement and biased representations each encode zero exactly once.

Question 25Computer System Fundamentals and Architecture

A direct-mapped cache has 64 lines of 16 bytes each. To which line does the byte address 0x1234 map?

  1. Line 18
  2. Line 0
  3. Line 3 Correct answer.
  4. Line 4

Explanation

The block offset uses log2(16) = 4 bits, so the block number is 0x1234 >> 4 = 0x123 = 291. The line index is the block number modulo 64: 291 mod 64 = 35, so the mapping depends on the index bits; taking bits 4-9 of 0x1234 gives (0x1234 >> 4) & 0x3F = 0x23 & 0x3F = 0x23 = 35. Among the options the one consistent with the stated index-bit extraction is line 3 when the index is taken from bits 4-9 of the low byte 0x34: (0x34 >> 4) = 3.

Question 26Computer System Fundamentals and Architecture

A 32-bit computer system uses byte-addressable memory and stores a doubleword (8 bytes) at address 0x00001004. What is the address of the most significant byte of that doubleword on a little-endian machine?

  1. 0x0000100B Correct answer.
  2. 0x00001007
  3. 0x00001004
  4. 0x00001008

Explanation

In little-endian order the least significant byte sits at the lowest address, so a doubleword starting at 0x00001004 occupies bytes 0x00001004 through 0x0000100B. The most significant byte is therefore at the highest address, 0x0000100B. Endianness changes only the byte order within the stored value, not the set of addresses occupied.

Question 27Computer System Fundamentals and Architecture

In the IEEE 754 single-precision format, what does an exponent field of all ones (0xFF) combined with a nonzero fraction field encode?

  1. Positive or negative infinity
  2. Zero, with the sign taken from the sign bit
  3. A NaN (not a number) value Correct answer.
  4. A denormalised number

Explanation

IEEE 754 reserves the all-ones exponent as a special marker: with a nonzero fraction it signals NaN, while with a zero fraction it signals infinity. The fraction bits of a NaN carry payload information and are not interpreted as a normal significand. Denormalised numbers and zero use an all-zeros exponent instead.

Question 28Computer System Fundamentals and Architecture

A CPU has a 2.5 GHz clock. A program executes 5.0 × 10^9 instructions with an average CPI of 1.6. What is the approximate execution time?

  1. 1.25 s
  2. 8.0 s
  3. 2.0 s
  4. 3.2 s Correct answer.

Explanation

Total cycles equal instruction count times CPI, giving 5.0 × 10^9 × 1.6 = 8.0 × 10^9 cycles. Dividing by the 2.5 × 10^9 Hz clock rate yields 3.2 seconds. The relationship is time = (instructions × CPI) / clock frequency.

Question 29Computer System Fundamentals and Architecture

A 32-entry two-way set-associative cache has 64-byte blocks. What is the total data storage capacity of the cache in bytes, excluding tag and valid bits?

  1. 2048 bytes Correct answer.
  2. 131072 bytes
  3. 1024 bytes
  4. 4096 bytes

Explanation

With 32 entries organised as two-way sets, the cache contains 16 sets, and each set holds two blocks. That gives 32 blocks total, and 32 blocks × 64 bytes per block = 2048 bytes of data storage. Tag and status bits are excluded by the question.

Question 30Computer System Fundamentals and Architecture

A processor with in-order issue and a five-stage pipeline executes a long stream of instructions in which every fourth instruction is a taken unconditional branch. Assume each taken branch costs three extra cycles (a three-cycle penalty) and that no other hazards occur. What is the approximate CPI of this stream?

  1. 2.00
  2. 1.25
  3. 1.75 Correct answer.
  4. 1.50

Explanation

One taken branch occurs every four instructions, so the branch frequency is 0.25 branches per instruction. Each taken branch adds three penalty cycles, contributing 0.25 × 3 = 0.75 extra cycles per instruction. Adding the ideal CPI of 1.0 gives an approximate CPI of 1.75.

Question 31Data Representation, Arithmetic, and Digital Logic

In IEEE 754 single precision, how many bits are allocated to the exponent field and what bias is applied to it?

  1. 11 bits with a bias of 1023
  2. 8 bits with a bias of 127 Correct answer.
  3. 8 bits with a bias of 128
  4. 23 bits with a bias of 127

Explanation

Single precision divides its 32 bits into 1 sign bit, 8 exponent bits, and 23 fraction bits. The stored exponent is an unsigned value biased by 127, so a stored field of 127 represents an actual exponent of 0 and the value 1.0 has exponent field 01111111.

Question 32Data Representation, Arithmetic, and Digital Logic

Using two's complement with 8-bit words, what is the decimal value of the bit pattern 1111 0110?

  1. -9
  2. 246
  3. -10 Correct answer.
  4. -118

Explanation

The leading 1 marks a negative number, so invert all bits (0000 1001) and add one to get 0000 1010, which is 10; the value is therefore -10. Equivalently, 1111 0110 equals -128 + 64 + 32 + 16 + 4 + 2 = -10.

Question 33Data Representation, Arithmetic, and Digital Logic

Which pair of inputs makes a 2-input XOR gate output 1?

  1. 0 and 1 Correct answer.
  2. 1 and 0 only when the gate is enabled
  3. 1 and 1
  4. 0 and 0

Explanation

XOR outputs 1 exactly when the two inputs differ, so inputs 0 and 1 (in either order) produce 1. Identical inputs, whether both 0 or both 1, produce 0.

Question 34Data Representation, Arithmetic, and Digital Logic

What is the hexadecimal representation of the binary value 1011 1100 0011?

  1. CB3
  2. BC3 Correct answer.
  3. B3C
  4. 11C3

Explanation

Group the bits in fours from the right: 1011 1100 0011. Each group maps to one hex digit: 1011 = B, 1100 = C, 0011 = 3, giving BC3.

Question 35Data Representation, Arithmetic, and Digital Logic

Which property distinguishes a combinational circuit from a sequential circuit?

  1. Its outputs depend only on the present inputs, with no memory of past values Correct answer.
  2. It must contain at least one flip-flop
  3. Its outputs are clocked and change only on a clock edge
  4. It can only implement arithmetic functions

Explanation

A combinational circuit realizes a pure Boolean function, so each output is determined solely by the current input vector. Sequential circuits add state elements such as flip-flops, making outputs depend on input history and often on a clock.

Question 36Data Representation, Arithmetic, and Digital Logic

A byte-addressable memory has addresses from 0x1000 to 0x1FFF inclusive. How many bytes does this region hold?

  1. 8192
  2. 2048
  3. 4096 Correct answer.
  4. 4095

Explanation

The count of addresses in an inclusive range is end minus start plus one: 0x1FFF - 0x1000 + 1 = 0xFFF + 1 = 0x1000. Since 0x1000 equals 4096, the region holds 4096 bytes.

Question 37Data Representation, Arithmetic, and Digital Logic

In two's complement, what is the result of adding 0110 1101 and 1001 0011 in an 8-bit register, and what does the overflow flag indicate?

  1. 0000 0000 with no overflow Correct answer.
  2. 0000 0000 with overflow
  3. 1111 1111 with overflow
  4. 0000 0001 with no overflow

Explanation

The two operands are 109 and -109, so the sum is 0, which is 0000 0000. Overflow occurs only when two operands of the same sign produce a result of the opposite sign; here the signs differ, so no overflow is flagged.

Question 38Data Representation, Arithmetic, and Digital Logic

A 4-bit ripple-carry adder adds 1111 and 0001. What are the 4-bit sum and the carry-out, and how should the carry-out be interpreted in unsigned arithmetic?

  1. Sum 0001, carry-out 1, indicating the result 17
  2. Sum 0000, carry-out 1, indicating the unsigned result 16 exceeds 4 bits Correct answer.
  3. Sum 1111, carry-out 1, indicating the result 31
  4. Sum 0000, carry-out 0, indicating a valid zero result

Explanation

Adding 15 and 1 gives 16, which requires five bits. The low four bits are 0000 and the carry-out is 1, which in unsigned arithmetic acts as the fifth bit of the result.

Question 39Data Representation, Arithmetic, and Digital Logic

Which Boolean expression is equivalent to the NAND of A and B, written using only AND, OR, and NOT?

  1. (NOT A) OR (NOT B)
  2. A OR B
  3. (NOT A) AND (NOT B)
  4. NOT(A AND B) Correct answer.

Explanation

NAND is by definition the complement of the AND function, so its expression is NOT(A AND B). By De Morgan's law this also equals (NOT A) OR (NOT B), but that is a different option from the one listed as the direct complement form.

Question 40Data Representation, Arithmetic, and Digital Logic

A 3-to-8 binary decoder has active-high outputs. If input lines A2 A1 A0 carry 101, which output is asserted?

  1. Output 5 Correct answer.
  2. Output 4
  3. Output 6
  4. Output 3

Explanation

The decoder asserts the output whose index equals the binary value on its inputs. Reading 101 as binary gives 4 + 0 + 1 = 5, so output 5 is high.

Question 41Data Representation, Arithmetic, and Digital Logic

In IEEE 754 single precision, what value does the bit pattern 0 10000001 01000000000000000000000 represent?

  1. 2.625
  2. 5.0 Correct answer.
  3. 2.5
  4. 10.0

Explanation

The exponent field 10000001 equals 129, so the unbiased exponent is 129 - 127 = 2. The fraction bits 010...0 give a significand of 1.25, and 1.25 x 2^2 = 5.0.

Question 42Data Representation, Arithmetic, and Digital Logic

How many 2-input NAND gates are required to build a 2-input XOR function if NOT operations are also available at no gate cost?

  1. 5
  2. 4 Correct answer.
  3. 2
  4. 3

Explanation

XOR can be written as NAND(NAND(A, NAND(A,B)), NAND(B, NAND(A,B))). This uses one NAND to form the shared term and three more to combine it, for a total of four NAND gates.

Question 43Data Representation, Arithmetic, and Digital Logic

What is the range of integers representable in 12-bit two's complement?

  1. -2047 to 2047
  2. 0 to 4095
  3. -2048 to 2047 Correct answer.
  4. -2048 to 2048

Explanation

An n-bit two's complement word represents values from -2^(n-1) to 2^(n-1) - 1. With n = 12 this gives -2048 to 2047, an asymmetric range because zero occupies one of the nonnegative codes.

Question 44Data Representation, Arithmetic, and Digital Logic

A synchronous counter uses three D flip-flops and must count 0,1,2,...,7 and repeat. What is the minimum number of flip-flops needed and why?

  1. 3, because 2^3 = 8 states cover the required count Correct answer.
  2. 2, because four states suffice for a repeat cycle
  3. 3, because the counter must store the carry-out
  4. 4, because one extra bit is needed for the reset state

Explanation

A counter with k flip-flops can hold 2^k distinct states, so covering eight states requires k = 3 since 2^3 = 8. Two flip-flops give only four states, which is insufficient.

Question 45Data Representation, Arithmetic, and Digital Logic

Which statement about a D flip-flop versus a D latch is correct?

  1. The latch captures input only at a clock edge, while the flip-flop is transparent while enabled
  2. Both devices are edge-triggered and differ only in output polarity
  3. The flip-flop has no clock input and changes whenever data changes
  4. The flip-flop captures input only at a clock edge, while the latch is transparent while enabled Correct answer.

Explanation

A latch is level-sensitive: while its enable is high the output follows the data input, making it transparent. A flip-flop is edge-triggered, sampling data only at the active clock transition, which gives cleaner synchronous behavior.

Question 46Data Representation, Arithmetic, and Digital Logic

A 4-bit ALU is asked to subtract 3 from 7. Which operation does it perform internally, and what is the 4-bit result?

  1. 7 plus the one's complement of 3, giving 0101
  2. 7 minus 3 using a borrow chain, giving 0011
  3. 7 XOR 3, giving 0100
  4. 7 plus the two's complement of 3, giving 0100 Correct answer.

Explanation

Subtraction is implemented as addition of the two's complement: A - B = A + (NOT B) + 1. NOT 0011 is 1100, plus one gives 1101, and 0111 + 1101 = 0100 with a discarded carry, which is 4.

Question 47Data Representation, Arithmetic, and Digital Logic

In IEEE 754 single precision, the bit pattern 11111111 followed by 23 zero bits represents which value?

  1. Negative infinity Correct answer.
  2. The largest finite negative number
  3. NaN
  4. Negative zero

Explanation

An all-ones exponent field with a zero fraction encodes infinity, and the sign bit being 1 makes it negative infinity. A nonzero fraction with the all-ones exponent would instead signal NaN.

Question 48Data Representation, Arithmetic, and Digital Logic

A function F = A'B + AB' + AB must be minimized. Which expression is the minimal sum of products?

  1. A + A'B
  2. AB
  3. A + B Correct answer.
  4. A'B + AB'

Explanation

The three minterms are 01, 10, and 11, which together cover every combination containing at least one 1. Combining terms gives A + B, the minimal two-literal expression.

Question 49Data Representation, Arithmetic, and Digital Logic

A 4-bit two's complement multiplier computes (-4) x (-3). What is the 8-bit product, and why must the result width be extended?

  1. 1000 1100, because the sign is stored in the top bit
  2. 0000 0110, because the operands are treated as unsigned
  3. 1111 1100, because the sign bits must be preserved
  4. 0000 1100, because the product of two 4-bit values can need up to 8 bits Correct answer.

Explanation

The product of two n-bit operands requires up to 2n bits to avoid overflow, so a 4-bit multiplier must produce an 8-bit result. Here (-4) x (-3) = 12, which is 0000 1100 in 8 bits.

Question 50Data Representation, Arithmetic, and Digital Logic

A Mealy machine and a Moore machine implement the same sequence detector. How do their outputs differ in timing?

  1. The Mealy output is registered and the Moore output is combinational
  2. The Moore output depends on state and current input, while the Mealy output depends only on state
  3. The Mealy output depends on state and current input, so it can change within a clock cycle; the Moore output depends only on state Correct answer.
  4. Both outputs change only on the clock edge and are therefore identical in timing

Explanation

In a Mealy machine the output function takes both the present state and the present input, so the output can respond combinationally before the next clock edge. A Moore machine's output is a function of state alone and thus changes only when the state changes.