Computer System Fundamentals and Architecture
Computer System Fundamentals and Architecture tests how a program becomes execution: CPU organization, instruction cycles, memory hierarchy, and the quantitative reasoning used to compare designs. Expect definitions plus small calculations rather than deep hardware design.
Core model
A stored-program machine fetches an instruction, decodes it, executes it, and writes results back. Pipelining overlaps these stages; hazards (data, control, structural) are handled by forwarding, stalls, or branch prediction. Caches exploit locality: L1 is small and fast, L3 is large and shared. Performance is instructions × cycles per instruction × clock period, so reducing any factor helps.
Worked example
An instruction mix is 50% ALU (CPI 1), 30% load/store (CPI 4), and 20% branch (CPI 2). Average CPI = 0.50×1 + 0.30×4 + 0.20×2 = 2.1. At 2 GHz, execution rate is 2,000 Mcycles/s ÷ 2.1 ≈ 952 MIPS for this mix. The load/store class dominates the average despite being only 30% of instructions.
Traps
Do not average the CPIs without weighting by instruction frequency, and do not treat cache hit time as miss penalty. Amdahl's law applies to the fraction actually improved: speeding up a 40% portion by 4× gives 1/(0.6 + 0.4/4) = 1.43×, not 4×. Also distinguish latency from throughput and RISC from CISC by design philosophy, not by one instruction count.