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MATSEC AM Computing study materials
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MATSEC AM Computing practice questions

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Question 1Computer Systems and Architecture

In the von Neumann architecture, which unit is responsible for fetching and decoding each instruction before it is executed?

  1. The memory data register
  2. The control unit Correct answer.
  3. The accumulator
  4. The arithmetic logic unit

Explanation

The control unit coordinates the fetch-decode-execute cycle by generating the control signals that move instructions from memory and decode their operation codes. The ALU performs arithmetic and logic operations but does not direct instruction sequencing.

Question 2Computer Systems and Architecture

A binary number is stored in an 8-bit register. Which range of unsigned integer values can it represent?

  1. 0 to 255 Correct answer.
  2. -128 to 127
  3. 0 to 256
  4. 1 to 256

Explanation

An 8-bit unsigned register has 2^8 = 256 distinct bit patterns, which map to the values 0 through 255 inclusive. The range -128 to 127 applies only when two's complement signed interpretation is used.

Question 3Computer Systems and Architecture

Which statement best describes the role of cache memory in a computer system?

  1. It stores frequently accessed data close to the CPU to reduce average memory access time Correct answer.
  2. It holds the contents of virtual memory when RAM is exhausted
  3. It buffers data travelling between the CPU and peripheral devices
  4. It permanently stores the bootstrap program that starts the machine

Explanation

Cache is a small, fast memory placed between the CPU and main memory that keeps recently or frequently used blocks, exploiting locality of reference to lower average access time. It is volatile and much smaller than main memory.

Question 4Computer Systems and Architecture

What is the principal advantage of using a RISC instruction set compared with a CISC instruction set?

  1. Simpler instructions that are easier to pipeline and typically execute in a single cycle Correct answer.
  2. Direct support for complex high-level operations such as string search in hardware
  3. A smaller number of instructions is required to implement any given program
  4. Reduced dependence on registers because operands may come directly from memory

Explanation

RISC designs use a small set of simple, fixed-length instructions that suit pipelining and often complete in one clock cycle. CISC instead favours fewer but more complex instructions, so a RISC program usually needs more instructions, not fewer.

Question 5Computer Systems and Architecture

Which logic gate produces a HIGH output only when all of its inputs are HIGH?

  1. AND Correct answer.
  2. XOR
  3. NAND
  4. OR

Explanation

An AND gate outputs 1 only for the input combination where every input is 1. An OR gate outputs 1 when at least one input is 1, and XOR outputs 1 only when the inputs differ.

Question 6Computer Systems and Architecture

Which type of memory is non-volatile and can be erased and reprogrammed electrically while still installed in a circuit?

  1. Flash memory Correct answer.
  2. A CPU register file
  3. Dynamic RAM
  4. Static RAM

Explanation

Flash memory retains its contents without power and can be erased and rewritten electrically in blocks, which is why it is used for firmware and solid-state storage. DRAM, SRAM and registers are all volatile.

Question 7Computer Systems and Architecture

In the fetch-decode-execute cycle, what is the function of the program counter?

  1. It holds the address of the next instruction to be fetched Correct answer.
  2. It holds the instruction currently being decoded
  3. It counts the number of clock cycles elapsed
  4. It stores the result of the most recent ALU operation

Explanation

The program counter stores the memory address of the next instruction so the control unit knows where to fetch from; it is incremented or overwritten by a branch. The instruction itself is held in the instruction register.

Question 8Computer Systems and Architecture

Which of the following is an example of system software rather than application software?

  1. An operating system kernel Correct answer.
  2. A photo editor
  3. A spreadsheet program
  4. A web browser

Explanation

System software manages the hardware and provides services for other programs; the operating system kernel is the core example. Spreadsheets, browsers and photo editors are application software written to perform user tasks.

Question 9Computer Systems and Architecture

The decimal value 45 is converted to 8-bit binary. Which bit pattern is correct?

  1. 00101011
  2. 00110101
  3. 01001101
  4. 00101101 Correct answer.

Explanation

45 = 32 + 8 + 4 + 1, so bits 5, 3, 2 and 0 are set, giving 00101101. Checking the place values confirms the sum equals 45.

Question 10Computer Systems and Architecture

A computer uses 12-bit memory addresses and each addressable word is 1 byte. What is the size of the addressable memory space?

  1. 2048 bytes
  2. 4096 bytes Correct answer.
  3. 1024 bytes
  4. 12288 bytes

Explanation

With 12 address bits there are 2^12 = 4096 distinct addresses, and at 1 byte per address the space is 4096 bytes. The other figures come from misapplying the exponent or multiplying by the bit width.

Question 11Computer Systems and Architecture

Using two's complement with 8 bits, what is the result of adding 0111 1111 and 0000 0001?

  1. 0000 0000, because the carry out is discarded
  2. 1000 0000, which is +128 and is a valid signed result
  3. 1111 1111, which is -1
  4. 1000 0000, which is -128 and indicates signed overflow Correct answer.

Explanation

Adding 127 and 1 gives the bit pattern 1000 0000 with a carry out of the sign position. In two's complement that pattern represents -128, so the sign has flipped incorrectly and signed overflow has occurred.

Question 12Computer Systems and Architecture

A CPU has a 16-bit instruction format: 4 bits for the opcode and 12 bits for the operand. How many distinct opcodes are available?

  1. 4
  2. 12
  3. 4096
  4. 16 Correct answer.

Explanation

The opcode field is 4 bits wide, so it can encode 2^4 = 16 distinct operation codes. The 12-bit operand field affects addressing capacity, not the number of opcodes.

Question 13Computer Systems and Architecture

Which statement correctly describes the difference between immediate and direct addressing modes?

  1. Immediate addressing always uses the program counter as the operand source
  2. Immediate addressing gives a memory address, while direct addressing embeds the operand in the instruction
  3. Both modes store the operand in a register specified by the instruction
  4. Immediate addressing embeds the operand in the instruction, while direct addressing gives the memory address of the operand Correct answer.

Explanation

In immediate addressing the operand value is part of the instruction itself, so no memory access is needed to fetch it. In direct addressing the instruction supplies the effective address at which the operand is found.

Question 14Computer Systems and Architecture

A cache has a hit rate of 90% and a hit time of 2 ns, while a miss costs 20 ns in total. What is the average memory access time?

  1. 4.0 ns
  2. 3.8 ns Correct answer.
  3. 11.0 ns
  4. 2.0 ns

Explanation

Average access time = hit time + miss rate x miss penalty = 2 + 0.1 x 20 = 2 + 2 = 4 ns... but with the miss penalty stated as total 20 ns the correct arithmetic gives 2 + (0.1 x 20) = 4.0 ns.

Question 15Computer Systems and Architecture

Why does a pipelined processor generally achieve higher throughput than an equivalent non-pipelined processor?

  1. Pipelining eliminates all data hazards automatically
  2. Each individual instruction completes with a shorter latency than in a non-pipelined design
  3. Several instructions are in different stages at the same time, so one instruction can complete each clock cycle Correct answer.
  4. The pipeline removes the need for a clock signal

Explanation

Pipelining overlaps the stages of different instructions so that, once the pipeline is full, an instruction can finish every cycle, raising throughput. Latency per instruction is not reduced, and hazards still require handling.

Question 16Computer Systems and Architecture

Which statement about interrupts is correct?

  1. An interrupt permanently halts the processor until the machine is restarted
  2. An interrupt suspends the current program so that a service routine can run, after which execution resumes Correct answer.
  3. An interrupt is handled by the ALU without involving the control unit
  4. An interrupt can only be raised by software, never by hardware

Explanation

When an interrupt is raised, the processor saves its state, transfers control to an interrupt service routine, and later restores the saved state to continue. Interrupts can be generated by hardware devices as well as by software.

Question 17Computer Systems and Architecture

Which memory hierarchy ordering correctly runs from fastest and smallest to slowest and largest?

  1. Cache, registers, main memory, magnetic disk
  2. Registers, cache, main memory, magnetic disk Correct answer.
  3. Registers, main memory, cache, magnetic disk
  4. Main memory, cache, registers, magnetic disk

Explanation

Access speed decreases and capacity increases as you move outward from the CPU: registers are fastest and smallest, followed by cache, then main memory, then secondary storage such as disk. This ordering exploits locality by keeping hot data close to the processor.

Question 18Computer Systems and Architecture

A Boolean function is given by F = A AND (NOT B). Which pair of input values makes F equal to 1?

  1. A = 1, B = 0 Correct answer.
  2. A = 0, B = 1
  3. A = 1, B = 1
  4. A = 0, B = 0

Explanation

For the AND of A with NOT B to be 1, both A and NOT B must be 1, which requires A = 1 and B = 0. Any other combination makes at least one input to the AND gate zero.

Question 19Computer Systems and Architecture

In a load-store architecture, which operations are permitted to access main memory?

  1. Only the branch instructions
  2. Only explicit load and store instructions Correct answer.
  3. Any instruction, provided the operand is aligned
  4. Any arithmetic instruction with a memory operand

Explanation

A load-store design restricts memory access to dedicated load and store instructions; all arithmetic and logic operations work on values already held in registers. This simplifies the pipeline and instruction decoding.

Question 20Computer Systems and Architecture

Which statement about the relationship between clock speed and performance is most accurate?

  1. A higher clock speed guarantees a shorter pipeline
  2. Clock speed has no effect on the time taken to execute a program
  3. Performance also depends on cycles per instruction and instruction count, not clock speed alone Correct answer.
  4. Doubling the clock frequency always doubles the execution time of a program

Explanation

Execution time equals instruction count x cycles per instruction x clock cycle time, so frequency is only one of three factors. A processor with a higher clock may still be slower if it needs more cycles per instruction.

Question 21Computer Systems and Architecture

An ALU is required to compute the two's complement of an 8-bit value. Which operation achieves this?

  1. Add 1 to the value without inverting any bits
  2. Shift the value one place to the left
  3. Invert all bits and then add 1 Correct answer.
  4. Invert all bits and then add 0

Explanation

The two's complement of a binary number is formed by flipping every bit (the one's complement) and adding one to the least significant bit. Inverting without adding one gives the one's complement, which differs by one.

Question 22Computer Systems and Architecture

A direct-mapped cache has 64 lines and main memory is byte-addressable with 16-bit addresses. If each line holds one 4-byte block, how many bits are used for the block offset and the line index respectively?

  1. 4 offset bits and 6 index bits
  2. 2 offset bits and 6 index bits Correct answer.
  3. 6 offset bits and 2 index bits
  4. 2 offset bits and 8 index bits

Explanation

A 4-byte block needs log2(4) = 2 offset bits to select a byte within the block. With 64 lines, log2(64) = 6 index bits select the line, leaving 8 bits for the tag.

Question 23Computer Systems and Architecture

A pipeline has five stages of 2 ns each, and 1 ns of register overhead is added between stages. What is the throughput once the pipeline is full?

  1. One instruction every 15 ns
  2. One instruction every 3 ns Correct answer.
  3. One instruction every 10 ns
  4. One instruction every 2 ns

Explanation

The pipeline clock period must cover the slowest stage plus the register overhead, so each stage takes 2 + 1 = 3 ns. Once full, one instruction leaves the pipeline per clock period, giving one every 3 ns.

Question 24Computer Systems and Architecture

A system uses 32-bit virtual addresses, 4 KiB pages and a single-level page table with one entry per page. How large is each page table in entries?

  1. 2^24 entries
  2. 2^32 entries
  3. 2^20 entries Correct answer.
  4. 2^12 entries

Explanation

A 4 KiB page has a 12-bit offset, leaving 32 - 12 = 20 bits of virtual page number, so the table needs 2^20 entries. The offset bits select a byte within a page and are not indexed in the table.

Question 25Computer Systems and Architecture

A CPU uses a 4-bit signed two's complement representation. What is the range of values it can represent?

  1. -8 to +8
  2. 0 to 15
  3. -8 to +7 Correct answer.
  4. -7 to +7

Explanation

With 4 bits there are 16 patterns; in two's complement one pattern (1000) represents -8 and the positive values run from 0 to 7, giving the asymmetric range -8 to +7. The range is asymmetric because zero occupies one pattern.

Question 26Computer Systems and Architecture

Which register in a processor holds the address of the next instruction to be fetched from memory?

  1. Memory data register (MDR)
  2. Instruction register (IR)
  3. Memory address register (MAR)
  4. Program counter (PC) Correct answer.

Explanation

The program counter holds the address of the next instruction; after each fetch it is incremented or loaded with a branch target. The MAR holds the address currently on the address bus, while the IR holds the fetched instruction itself.

Question 27Computer Systems and Architecture

Which of the following is an example of secondary storage rather than main memory?

  1. A DRAM module
  2. A register file
  3. A CPU cache
  4. A solid-state drive Correct answer.

Explanation

Secondary storage such as an SSD is non-volatile and retains data without power, and it is accessed through I/O subsystems rather than directly addressed as working memory. DRAM, cache and registers are all volatile storage inside the memory hierarchy used for active processing.

Question 28Computer Systems and Architecture

Which number base is used internally by digital computers because it maps directly onto two-state logic levels?

  1. Hexadecimal
  2. Binary Correct answer.
  3. Decimal
  4. Octal

Explanation

Binary uses only two symbols, 0 and 1, which correspond naturally to the two voltage levels of digital logic. Hexadecimal and octal are convenient shorthand for humans but are not the internal representation.

Question 29Computer Systems and Architecture

Which component of a stored-program computer performs arithmetic and logical operations on data?

  1. The input/output controller
  2. The memory management unit
  3. The arithmetic logic unit Correct answer.
  4. The control unit

Explanation

The arithmetic logic unit (ALU) carries out operations such as addition, subtraction, AND and OR on operands supplied to it. The control unit sequences operations but does not itself compute results.

Question 30Computer Systems and Architecture

In the von Neumann architecture, what is the key characteristic of the memory model?

  1. Instructions and data share a single address space and memory. Correct answer.
  2. Only data is stored in memory while instructions are hard-wired.
  3. Memory is addressed only by the control unit, never by the ALU.
  4. Instructions and data are held in separate, independently addressed memories.

Explanation

Von Neumann architecture stores both program instructions and data in the same memory, accessed over a shared path, which is why it is called a stored-program design. Harvard architecture, by contrast, separates instruction and data memories.

Question 31Computer Systems and Architecture

Which type of bus carries the address of the memory location or device that the processor wishes to access?

  1. The control bus
  2. The power bus
  3. The address bus Correct answer.
  4. The data bus

Explanation

The address bus is unidirectional and carries the location being selected for a read or write. The data bus carries the actual contents, while the control bus carries signals such as read/write and interrupt lines.

Question 32Computer Systems and Architecture

Which statement best describes the role of an operating system's scheduler?

  1. It stores files on the disk in contiguous blocks.
  2. It decides which ready process is allocated the CPU next. Correct answer.
  3. It translates virtual addresses into physical addresses.
  4. It compiles source code into machine instructions.

Explanation

The scheduler selects among ready processes and grants the CPU to one according to a scheduling policy such as round-robin or priority. Address translation is done by the memory management unit, and file placement is a file-system concern.

Question 33Computer Systems and Architecture

Convert the unsigned binary value 1011 0110 to hexadecimal.

  1. B4
  2. C6
  3. B6 Correct answer.
  4. A6

Explanation

Split the byte into two nibbles: 1011 is B and 0110 is 6, so the result is B6. Each hex digit corresponds to exactly four binary bits.

Question 34Computer Systems and Architecture

Using 8-bit two's complement, what is the decimal value of the bit pattern 1110 1100?

  1. 236
  2. -18
  3. -20 Correct answer.
  4. -19

Explanation

The leading bit is 1, so the value is negative; invert the bits to get 0001 0011 (19) and add 1, giving magnitude 20, hence -20. Alternatively, the place values are -128 + 64 + 32 + 8 + 4 = -20.

Question 35Computer Systems and Architecture

A 4-to-1 multiplexer has two select lines S1 and S0. Which input is routed to the output when S1 = 1 and S0 = 0?

  1. Input 3
  2. Input 0
  3. Input 2 Correct answer.
  4. Input 1

Explanation

The select lines form a binary number where S1 is the more significant bit, so S1S0 = 10 equals decimal 2, selecting input 2. A multiplexer forwards the selected input to its single output.

Question 36Computer Systems and Architecture

A byte-addressable memory has 20 address lines. What is the total capacity of the memory?

  1. 1 MB in decimal terms only
  2. 512 KiB
  3. 1 MiB Correct answer.
  4. 2 MiB

Explanation

Twenty address lines give 2^20 distinct addresses, and with one byte per address that is 1,048,576 bytes, which is 1 MiB. The mebibyte unit is appropriate because the size is a power of two.

Question 37Computer Systems and Architecture

Which statement correctly distinguishes RISC from CISC instruction sets?

  1. RISC processors cannot be pipelined, whereas CISC processors always are.
  2. RISC has many complex variable-length instructions, while CISC has few simple fixed-length ones.
  3. RISC favours a small set of simple fixed-length instructions, while CISC favours richer variable-length instructions. Correct answer.
  4. RISC instructions always access memory directly for arithmetic operands, while CISC never does.

Explanation

RISC designs favour a compact set of simple, usually fixed-length instructions that suit pipelining, whereas CISC designs provide many richer and often variable-length instructions. The load-store restriction belongs to RISC, not CISC.

Question 38Computer Systems and Architecture

In a CPU, what is the purpose of the status (flag) register?

  1. It stores the address of the next instruction.
  2. It buffers data travelling between the CPU and main memory.
  3. It holds the operand currently being decoded.
  4. It records condition bits such as zero, carry, sign and overflow from the last operation. Correct answer.

Explanation

The status register holds condition flags set by the ALU, such as zero, carry, sign and overflow, which conditional branch instructions test. It does not hold addresses or operands.

Question 39Computer Systems and Architecture

A hard disk has an average seek time of 8 ms, a rotational latency of 4 ms and a transfer time of 1 ms per block. What is the average time to read one block?

  1. 12 ms
  2. 9 ms
  3. 13 ms Correct answer.
  4. 5 ms

Explanation

The average access time is the sum of seek time, rotational latency and transfer time: 8 + 4 + 1 = 13 ms. All three delays occur in sequence for each block read.

Question 40Computer Systems and Architecture

Which statement about the relationship between cache associativity and performance is most accurate?

  1. Increasing associativity always increases the hit time and never reduces misses.
  2. Increasing associativity reduces conflict misses but generally increases hit time and comparison complexity. Correct answer.
  3. Increasing associativity removes compulsory misses for first-time accesses.
  4. Increasing associativity reduces capacity misses but has no effect on conflict misses.

Explanation

Higher associativity lets more blocks share a set, reducing conflict misses, but it requires more tag comparisons and multiplexing, which tends to raise hit time. Capacity and compulsory misses are unaffected by associativity.

Question 41Computer Systems and Architecture

What is the main purpose of virtual memory in a multitasking system?

  1. To increase the physical size of the RAM chips installed.
  2. To give each process an isolated address space that can exceed available physical memory. Correct answer.
  3. To make all memory accesses faster than cache accesses.
  4. To eliminate the need for a memory management unit.

Explanation

Virtual memory provides each process with its own protected address space and allows programs larger than physical RAM by paging to disk. It relies on the MMU and does not increase physical chip capacity.

Question 42Computer Systems and Architecture

Which of the following best describes the role of an interrupt handler?

  1. It is a compiler routine that expands macro instructions.
  2. It is a hardware circuit that generates clock pulses for the CPU.
  3. It is a routine that runs in response to a hardware or software interrupt to service the event. Correct answer.
  4. It is a program that permanently replaces the operating system scheduler.

Explanation

An interrupt handler is the routine the processor transfers control to when an interrupt is raised, so the event can be serviced before normal execution resumes. It runs within the operating system's interrupt framework and does not replace the scheduler.

Question 43Computer Systems and Architecture

A CPU executes 2 × 10^9 instructions in 0.5 seconds. What is its instruction throughput in millions of instructions per second (MIPS)?

  1. 4000 MIPS Correct answer.
  2. 2500 MIPS
  3. 1000 MIPS
  4. 2000 MIPS

Explanation

Throughput is instructions divided by time: 2 × 10^9 / 0.5 = 4 × 10^9 instructions per second, which is 4000 million instructions per second. Dividing by 10^6 converts to MIPS.

Question 44Computer Systems and Architecture

Which statement about the control unit's role in the fetch-decode-execute cycle is correct?

  1. It performs the arithmetic in the ALU on behalf of the datapath.
  2. It generates the control signals that coordinate the datapath during each cycle. Correct answer.
  3. It converts assembly language into machine code.
  4. It stores the program's instructions permanently in ROM.

Explanation

The control unit decodes the opcode and asserts the control signals that steer registers, the ALU and memory through each step. It directs the datapath rather than performing the arithmetic itself.

Question 45Computer Systems and Architecture

An 8-bit ADC has an input range of 0 V to 5 V. Approximately what input voltage corresponds to the digital output 1100 1000?

  1. 4.51 V
  2. 3.75 V
  3. 4.00 V
  4. 3.92 V Correct answer.

Explanation

The code 1100 1000 equals 200. The step size is 5 V / 255 ≈ 0.0196 V, so 200 × 0.0196 ≈ 3.92 V. Using the 255 divisor is correct for an 8-bit converter with 256 levels.

Question 46Computer Systems and Architecture

A processor has a 32-bit address space and a two-way set-associative cache with 64 KiB total data and 32-byte blocks. How many bits are used for the set index?

  1. 9 bits
  2. 10 bits Correct answer.
  3. 11 bits
  4. 8 bits

Explanation

With 64 KiB total and two ways, each way holds 32 KiB, giving 1024 lines per way. Each line holds 32 bytes, so there are 32 sets per way... correcting: 32 KiB / 32 B = 1024 blocks per way, and with two ways sharing a set, there are 1024 sets, requiring 10 index bits. The block offset uses 5 bits and the tag the remaining 17 bits.

Question 47Computer Systems and Architecture

A superscalar processor issues up to four instructions per cycle but achieves an average CPI of 0.5 on a program of 8 × 10^9 instructions. At 2 GHz, what is the approximate execution time?

  1. 2 s Correct answer.
  2. 4 s
  3. 1 s
  4. 0.5 s

Explanation

Cycles needed equal instructions × CPI = 8 × 10^9 × 0.5 = 4 × 10^9 cycles. At 2 × 10^9 cycles per second this gives 2 seconds. The issue width limits peak performance but the CPI already captures the achieved rate.

Question 48Computer Systems and Architecture

Which statement about the difference between a page fault and a cache miss is correct?

  1. Both are handled identically by the memory management unit without software.
  2. A page fault is serviced in hardware alone, while a cache miss requires operating system intervention.
  3. A page fault requires operating system involvement to bring a page from disk, while a cache miss is normally handled in hardware by fetching from lower memory. Correct answer.
  4. A cache miss always causes a page fault in the same access.

Explanation

A page fault occurs when a referenced page is not resident in physical memory, so the operating system must load it from disk, a comparatively slow software-involved process. A cache miss is normally resolved by hardware fetching the block from the next level of the hierarchy.

Question 49Computer Systems and Architecture

A five-stage pipeline has stage delays of 3 ns, 2 ns, 4 ns, 2 ns and 3 ns, with 1 ns register overhead between stages. What limits the steady-state clock period?

  1. The fastest stage plus register overhead, giving 3 ns.
  2. The average stage delay, which is 2.8 ns.
  3. The slowest stage plus register overhead, giving 5 ns. Correct answer.
  4. The sum of all stage delays, giving 14 ns.

Explanation

In a synchronous pipeline the clock period must accommodate the slowest stage because every stage must complete within one cycle, plus the register overhead, so 4 + 1 = 5 ns. Faster stages simply idle for part of the cycle.

Question 50Computer Systems and Architecture

Which statement about direct memory access (DMA) is correct?

  1. DMA is only possible when the device shares the CPU's register file.
  2. DMA eliminates the need for the system bus during transfers.
  3. DMA transfers data between a device and memory without the CPU copying each byte. Correct answer.
  4. DMA requires the CPU to execute an instruction for every byte transferred.

Explanation

A DMA controller moves blocks between a peripheral and memory directly, freeing the CPU from per-byte copying and raising it only when the transfer completes. The bus is still used, but by the DMA controller rather than the CPU.