Computer Systems and Architecture
What the domain tests
Computer Systems and Architecture examines how data is represented, how the CPU executes instructions, how memory is organised, and how I/O and performance are measured. Expect questions on binary and two’s complement, fetch–decode–execute, registers, addressing modes, cache, interrupts and von Neumann/Harvard models.
Core rules
- In an n-bit two’s complement system, values range from −2^(n−1) to 2^(n−1)−1. The most significant bit has weight −2^(n−1).
- The fetch–decode–execute cycle uses the program counter (PC), memory address register (MAR), memory data register (MDR), instruction register (IR) and accumulator/ALU.
- Cache exploits locality: temporal (reuse) and spatial (nearby addresses). Levels L1–L3 trade speed for size.
- RISC favours simple fixed-length instructions and many registers; CISC favours complex variable-length instructions.
- Performance is not clock speed alone: CPI, instruction count and cache/memory stalls matter.
Worked example
Represent −37 in 8-bit two’s complement. Write +37 as 0010 0101. Invert bits: 1101 1010. Add 1: 1101 1011. Check: MSB weight −128; remaining bits 64+16+8+2+1 = 91, so −128+91 = −37. Reasoning: inversion plus one gives the additive inverse in fixed-width two’s complement.
Traps
Do not sign-extend unsigned values; do not ignore overflow when adding two positives gives a negative; do not confuse MAR (address) with MDR (data); do not claim cache removes the need for RAM; do not treat clock rate as the only performance measure. Endianness affects byte order, not bit significance within a byte.