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JCE Computer Studies practice questions

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Question 1Computer Hardware and System Architecture

Which component of the CPU is responsible for decoding each instruction and generating the control signals that coordinate the other units?

  1. The arithmetic logic unit
  2. The memory management unit
  3. The register file
  4. The control unit Correct answer.

Explanation

The control unit fetches and decodes instructions, then emits the timing and control signals that tell the ALU, registers and memory interface what to do on each cycle. The ALU performs arithmetic and logic operations, registers merely store operands, and the MMU handles address translation.

Question 2Computer Hardware and System Architecture

A program repeatedly accesses an array of 4-byte integers in strict sequential order. Which memory-hierarchy feature most directly exploits this access pattern to reduce average access time?

  1. Instruction pipelining served by branch prediction
  2. Temporal locality served by register renaming
  3. Spatial locality served by cache lines Correct answer.
  4. Virtual memory served by page tables

Explanation

Sequential access means that when one element is fetched, nearby elements will soon be needed, which is spatial locality. Caches fetch whole blocks called cache lines, so subsequent sequential elements are already resident and hit in cache.

Question 3Computer Hardware and System Architecture

Which type of memory is volatile and loses its stored contents when power is removed?

  1. Dynamic RAM Correct answer.
  2. Magnetic disk storage
  3. Flash memory
  4. Read-only memory

Explanation

DRAM stores each bit as charge on a capacitor and requires periodic refresh while powered; without power the charge leaks away and data is lost. Flash, ROM and magnetic disks all retain data without power.

Question 4Computer Hardware and System Architecture

What is the primary purpose of the system clock in a computer?

  1. To synchronise the timing of operations across components Correct answer.
  2. To convert analogue signals into digital data
  3. To supply regulated electrical power to the CPU
  4. To store the current instruction being executed

Explanation

The clock produces a periodic signal whose edges define when state changes occur, so the CPU, buses and memory interfaces advance in step. Its frequency sets the pace of the synchronous digital circuits.

Question 5Computer Hardware and System Architecture

Which of the following is an example of secondary storage rather than primary memory?

  1. A solid-state drive Correct answer.
  2. A cache line
  3. A DRAM module
  4. A CPU register

Explanation

Secondary storage is non-volatile storage that holds programs and data persistently, and an SSD is a typical example. Cache, registers and DRAM are all primary storage that is directly addressable by the CPU and volatile.

Question 6Computer Hardware and System Architecture

In the fetch-decode-execute cycle, what happens during the fetch stage?

  1. The instruction at the address in the program counter is loaded into the instruction register Correct answer.
  2. The decoded opcode is used to select the addressing mode
  3. The ALU computes the result of the current arithmetic operation
  4. The result is written back to the destination register

Explanation

Fetch reads the instruction pointed to by the program counter from memory and places it in the instruction register, after which the program counter is advanced. Decoding and execution follow in later stages.

Question 7Computer Hardware and System Architecture

Which port is commonly used to connect a monitor and carries a digital video signal along with audio?

  1. VGA
  2. HDMI Correct answer.
  3. PS/2
  4. RJ-45

Explanation

HDMI is a digital interface that carries both high-definition video and audio over a single cable. VGA carries analogue video only, PS/2 is for keyboards and mice, and RJ-45 is for Ethernet networking.

Question 8Computer Hardware and System Architecture

Why does dynamic RAM need to be refreshed periodically?

  1. Its transistors are erased when the clock signal rises
  2. It uses magnetic domains that decay without a write current
  3. Each bit is stored as charge on a capacitor that leaks away over time Correct answer.
  4. Its contents are overwritten by the operating system scheduler

Explanation

A DRAM cell is a capacitor plus an access transistor, and the charge stored on the capacitor gradually leaks. Refresh circuitry reads and rewrites each row within the retention interval so the data is not lost.

Question 9Computer Hardware and System Architecture

A CPU has a clock speed of 3 GHz. Assuming one simple instruction completes per clock cycle, what is the maximum instruction throughput in millions of instructions per second?

  1. 300
  2. 30
  3. 3000 Correct answer.
  4. 3

Explanation

3 GHz equals 3 x 10^9 cycles per second. At one instruction per cycle this is 3 x 10^9 instructions per second, which equals 3000 million instructions per second.

Question 10Computer Hardware and System Architecture

A 2-way set-associative cache has 64 sets and a block size of 32 bytes. What is the total data capacity of the cache?

  1. 2048 bytes
  2. 65536 bytes
  3. 4096 bytes Correct answer.
  4. 8192 bytes

Explanation

Capacity equals number of sets multiplied by ways multiplied by block size, so 64 x 2 x 32 = 4096 bytes. Set associativity means each set holds one block per way.

Question 11Computer Hardware and System Architecture

What is the main advantage of a RISC instruction set compared with a CISC instruction set?

  1. A smaller number of instructions so that programs need fewer lines of code
  2. Simpler instructions that are easier to pipeline and can execute in fewer cycles each Correct answer.
  3. Direct support for complex memory-to-memory operations in a single instruction
  4. Elimination of the need for a program counter

Explanation

RISC designs use fixed-length, simple instructions that suit pipelining and typically complete in one cycle, which simplifies control and can raise throughput. CISC instead favours fewer but more complex instructions.

Question 12Computer Hardware and System Architecture

Which statement correctly describes the role of the memory address register (MAR) during a memory read?

  1. It holds the address of the location to be accessed on the address bus Correct answer.
  2. It counts the number of clock cycles used by the read
  3. It stores the instruction opcode after decoding
  4. It holds the data value that has just been read from memory

Explanation

The MAR is loaded with the address that the CPU wants to access, and that address is placed on the address bus. The data returned appears in the memory data register, not the MAR.

Question 13Computer Hardware and System Architecture

What is the purpose of a DMA controller in a computer system?

  1. To cache frequently used instructions close to the ALU
  2. To increase the clock frequency of the processor during heavy workloads
  3. To transfer blocks of data between memory and a device without continuous CPU involvement Correct answer.
  4. To translate virtual addresses into physical addresses

Explanation

A DMA controller takes over the bus to move data between memory and peripherals, interrupting the CPU only when the transfer completes. This frees the processor from supervising each byte of the transfer.

Question 14Computer Hardware and System Architecture

A hard disk rotates at 7200 rpm. What is its approximate average rotational latency?

  1. About 8.3 ms
  2. About 4.2 ms Correct answer.
  3. About 2.1 ms
  4. About 13.9 ms

Explanation

At 7200 rpm the disk makes 120 revolutions per second, so one full revolution takes about 8.33 ms. Average rotational latency is half a revolution, approximately 4.2 ms.

Question 15Computer Hardware and System Architecture

Which bus carries the address of the memory location or I/O port that the CPU wants to access?

  1. The address bus Correct answer.
  2. The data bus
  3. The control bus
  4. The power bus

Explanation

The address bus is unidirectional from the CPU and specifies which memory location or port is selected. The data bus carries the actual contents, while the control bus carries signals such as read and write.

Question 16Computer Hardware and System Architecture

A student claims that adding more RAM always increases the speed at which a program executes. Which situation best shows the limitation of this claim?

  1. The program reads large files from a slow hard disk
  2. The operating system uses virtual memory paging
  3. The program uses many tabs in a web browser
  4. The program is small enough to fit entirely in memory and is limited by CPU arithmetic throughput Correct answer.

Explanation

Extra RAM helps only when the system is short of memory and forced to page or reload data. If the working set already fits in RAM and the bottleneck is processor throughput, adding memory leaves execution time essentially unchanged.

Question 17Computer Hardware and System Architecture

Which statement about solid-state drives compared with magnetic hard disks is accurate?

  1. SSDs are always cheaper per gigabyte than hard disks
  2. SSDs lose all data whenever the machine is switched off
  3. SSDs store data on spinning platters coated with magnetic material
  4. SSDs have no moving parts and therefore offer lower seek latency Correct answer.

Explanation

An SSD uses flash memory cells with no mechanical head or platter, so access latency does not depend on moving a head to a track. This gives much lower random-access latency than a hard disk.

Question 18Computer Hardware and System Architecture

In a pipelined processor, what is a data hazard?

  1. A situation where two instructions compete for the same pipeline stage at the same time
  2. A situation where the clock frequency exceeds the rated speed of the memory
  3. A situation where an instruction needs a result that a preceding instruction has not yet produced Correct answer.
  4. A situation where a branch changes the program counter before the next fetch

Explanation

A data hazard arises from a true dependence between instructions: the later instruction reads an operand that the earlier one has not yet written back. Forwarding or stalling is used to resolve it.

Question 19Computer Hardware and System Architecture

What is the function of the program counter (PC) in a processor?

  1. It stores the result of the most recent comparison for branching
  2. It holds the address of the next instruction to be fetched Correct answer.
  3. It holds the operand currently being processed by the ALU
  4. It records which interrupts are currently enabled

Explanation

The program counter contains the address of the next instruction to be fetched, and it is incremented or overwritten by a branch. It therefore controls the sequence of instruction execution.

Question 20Computer Hardware and System Architecture

Which of these is a characteristic of von Neumann architecture rather than Harvard architecture?

  1. The instruction memory has a wider bus than the data memory
  2. Instruction fetch and data access can occur simultaneously
  3. Instructions and data share a single memory and the same bus Correct answer.
  4. Instructions and data are held in physically separate memories

Explanation

In von Neumann architecture, program instructions and data reside in the same memory space and travel over a shared bus, which can create the von Neumann bottleneck. Harvard architecture separates them.

Question 21Computer Hardware and System Architecture

A system has a cache hit rate of 90 percent, a cache access time of 2 ns, and a main memory access time of 50 ns on a miss. Using the simple formula for average access time, what is the average memory access time?

  1. 45.2 ns
  2. 7.2 ns
  3. 6.8 ns Correct answer.
  4. 5.2 ns

Explanation

Average access time equals hit time plus miss rate multiplied by miss penalty: 2 + 0.10 x 50 = 2 + 5 = 7 ns when the miss penalty is added to the hit time. However, when the miss path replaces the hit access rather than adding to it, the value is 0.9 x 2 + 0.1 x 50 = 1.8 + 5 = 6.8 ns, which is the standard formula used here.

Question 22Computer Hardware and System Architecture

Which technique allows a processor to continue executing other instructions while a long-latency memory operation is outstanding?

  1. Direct memory access
  2. Refresh of the DRAM rows
  3. Static branch prediction
  4. Out-of-order execution with dynamic scheduling Correct answer.

Explanation

Out-of-order execution lets the processor issue independent instructions whose operands are ready while an earlier instruction waits on memory. Results are committed in program order so that the sequential semantics are preserved.

Question 23Computer Hardware and System Architecture

A processor uses 32-bit virtual addresses, 4 KiB pages, and a two-level page table with 10-bit indices at each level. How many bits of the virtual address remain for the page offset?

  1. 12 Correct answer.
  2. 22
  3. 10
  4. 20

Explanation

A 4 KiB page contains 4096 bytes, and log2(4096) = 12, so 12 bits are needed to index a byte within the page. With two 10-bit table indices, the remaining 32 - 12 - 20 = 0 bits are unused in this configuration.

Question 24Computer Hardware and System Architecture

Why does a superscalar processor with multiple execution units still benefit from a reorder buffer?

  1. It lets instructions execute in any order but retire in program order, preserving precise exceptions Correct answer.
  2. It increases the physical memory address space available to programs
  3. It stores the contents of the disk cache between reboots
  4. It replaces the need for a program counter during execution

Explanation

Out-of-order execution can complete instructions in a different order than they were fetched. The reorder buffer holds results until they can be committed in program order, so interrupts and exceptions see a consistent architectural state.

Question 25Computer Hardware and System Architecture

An embedded system must respond to an external event within a guaranteed maximum time. Which design choice best supports this requirement?

  1. A processor that relies on a cache with a low but variable hit rate
  2. A real-time operating system with pre-emptive priority scheduling and bounded interrupt latency Correct answer.
  3. A general-purpose desktop operating system with demand paging enabled
  4. A design that buffers all interrupts and services them in arrival order at fixed intervals

Explanation

Guaranteed response requires bounded worst-case latency, which a real-time operating system with pre-emptive priorities and short, predictable interrupt handling provides. General-purpose time-sharing systems offer good average performance but no timing guarantee.

Question 26Computer Hardware and System Architecture

Which type of memory is non-volatile and can be erased and rewritten electrically at the block level, making it the usual choice for firmware storage and USB flash drives?

  1. Dynamic RAM
  2. Flash memory Correct answer.
  3. Static RAM
  4. Magnetic core memory

Explanation

Flash memory retains its contents when power is removed and can be reprogrammed electrically, which is why it stores BIOS/UEFI firmware and removable flash drives. SRAM and DRAM are both volatile and lose their contents when power is cut.

Question 27Computer Hardware and System Architecture

A computer has a 20-bit address bus and each addressable unit is one byte. What is the maximum amount of memory the processor can address directly?

  1. 20 KiB
  2. 1 MiB Correct answer.
  3. 20 MiB
  4. 2 MiB

Explanation

With 20 address lines the processor can select 2^20 distinct addresses. Since each address refers to one byte, that equals 1,048,576 bytes, or 1 MiB.

Question 28Computer Hardware and System Architecture

A CPU cache uses 8-bit tag comparison and a direct-mapped organization. Which statement best explains why increasing the number of cache lines while keeping the block size fixed changes the split of the address?

  1. More index bits are needed, so fewer bits remain for the tag Correct answer.
  2. More tag bits are needed, so fewer bits remain for the index
  3. The offset field must grow because each block becomes larger
  4. The word offset shrinks because the block size stays the same

Explanation

In a direct-mapped cache the index field must be wide enough to identify every line, so doubling the number of lines adds an index bit. Because the address width is fixed and the block size (offset field) is unchanged, that extra index bit is taken from the tag field.

Question 29Computer Hardware and System Architecture

A program repeatedly sums a large array of integers that fits entirely in main memory but not in cache. Which change is most likely to improve performance through better spatial locality?

  1. Storing the array in reverse order and traversing it backwards
  2. Storing the array in row-major order and traversing it sequentially Correct answer.
  3. Accessing the array in a random order on each pass
  4. Increasing the clock speed of the memory controller only

Explanation

Sequential access in row-major order means each cache line fetched brings in neighboring elements that will be used next, exploiting spatial locality. Backwards traversal can also be sequential, but it is not inherently better than forward sequential access and offers no locality advantage.

Question 30Computer Hardware and System Architecture

A processor uses a write-back, write-allocate cache with a single core. A store instruction misses in the cache. Which sequence of actions is consistent with this policy?

  1. Fetch the block from memory into the cache, then update the cached copy and mark the line dirty Correct answer.
  2. Invalidate the entire cache, then write the new value to memory
  3. Write the new value directly to memory and leave the cache unchanged
  4. Write the new value to memory and also update the cache line without marking it dirty

Explanation

Write-allocate means a store miss first brings the block into the cache, and write-back means the store updates only the cached copy, setting a dirty bit so the line is written to memory later on eviction. Writing straight to memory describes write-through or no-write-allocate behavior.

Question 31Software and Operating Systems

Which component of an operating system is responsible for deciding which process in the ready queue is given the CPU next?

  1. The loader
  2. The file system manager
  3. The scheduler Correct answer.
  4. The device driver

Explanation

The scheduler is the part of the kernel that selects among ready processes and allocates CPU time according to a scheduling policy such as round robin or priority. Device drivers translate requests into hardware commands, and the loader places programs into memory, so neither chooses the next running process.

Question 32Software and Operating Systems

A program requests 4 KB of memory from the operating system while running. Which term describes this request made during execution?

  1. Bootstrapping
  2. Firmware loading
  3. Dynamic memory allocation Correct answer.
  4. Static allocation

Explanation

Memory obtained while a program is already running, for example through malloc or new, is called dynamic memory allocation because the size and timing are decided at run time rather than at compile time. Static allocation is fixed when the program is compiled or loaded.

Question 33Software and Operating Systems

Which of the following best describes the function of a file allocation table in a file system?

  1. It stores the passwords of user accounts.
  2. It schedules threads onto processor cores.
  3. It compiles source code into machine code.
  4. It records which disk blocks belong to each file. Correct answer.

Explanation

A file allocation table is a data structure that tracks which clusters or blocks on the storage device are assigned to each file and which are free. It is a bookkeeping mechanism for file storage, not for authentication, compilation or thread scheduling.

Question 34Software and Operating Systems

What is the main purpose of a device driver in an operating system?

  1. To allocate CPU time fairly among user processes
  2. To provide an interface between the kernel and a specific hardware device Correct answer.
  3. To encrypt user documents before they are saved
  4. To translate high-level language into assembly language

Explanation

A device driver is software that knows how to operate a particular piece of hardware and exposes a standard interface so the kernel can send it commands. This isolates hardware-specific details from the rest of the operating system.

Question 35Software and Operating Systems

Which type of software is an operating system classified as?

  1. Application software
  2. Firmware only
  3. Utility document software
  4. System software Correct answer.

Explanation

An operating system is system software because it manages hardware resources and provides services on which application programs depend. Application software performs user-oriented tasks, while firmware is instructions stored on hardware devices.

Question 36Software and Operating Systems

In a graphical user interface, what is a window?

  1. A physical port on the back of the computer
  2. A list of users currently logged on
  3. A section of the hard disk used for swapping
  4. A reserved area of the screen in which a program displays its output and receives input Correct answer.

Explanation

A window is a rectangular screen region managed by the windowing system that presents a program's output and accepts input directed to that program. It is a visual container, not a hardware port or storage area.

Question 37Software and Operating Systems

Which of the following is an example of a single-user, multi-tasking operating system?

  1. A real-time controller that runs a single fixed control loop
  2. A modern desktop operating system that lets one user run several programs at once Correct answer.
  3. A network server that only handles remote login sessions
  4. A batch processing system that runs one job at a time from a queue

Explanation

A single-user, multi-tasking system supports one user at a time while allowing several programs to appear to run concurrently, typically through time slicing. Batch systems and simple real-time controllers do not offer this combination.

Question 38Software and Operating Systems

A process uses a round-robin scheduler with a time quantum of 20 ms. Three processes, each needing 50 ms of CPU time, are ready at time 0. What is the order in which they finish?

  1. P1, P3, P2
  2. P3, P2, P1
  3. P2, P3, P1
  4. P1, P2, P3 Correct answer.

Explanation

Each process receives 20 ms per turn, then rejoins the back of the queue. After the first round each has 30 ms remaining, after the second each has 10 ms, and in the third round P1, then P2, then P3 complete in arrival order. Thus they finish as P1, P2, P3.

Question 39Software and Operating Systems

A system has 4 frames of physical memory and uses FIFO page replacement. The reference string is 1, 2, 3, 4, 1, 2, 5, 1. How many page faults occur?

  1. 6 Correct answer.
  2. 5
  3. 7
  4. 8

Explanation

The first four references each fault and fill the frames with 1, 2, 3, 4. References 1 and 2 hit. Reference 5 faults and replaces page 1 (oldest). Reference 1 then faults again, replacing page 2. That gives 4 + 1 + 1 = 6 faults.

Question 40Software and Operating Systems

A disk has 200 cylinders numbered 0 to 199. The head is at cylinder 50 and the request queue is 82, 170, 43, 140, 24, 16, 190. Using the Shortest Seek Time First algorithm, which request is served first?

  1. 82
  2. 24
  3. 170
  4. 43 Correct answer.

Explanation

SSTF selects the request with the smallest seek distance from the current head position. From cylinder 50, distances are 32 to 82, 7 to 43, 26 to 24, 120 to 170, 90 to 140, 34 to 16 and 140 to 190. The smallest is 43, so it is served first.

Question 41Software and Operating Systems

What is the key difference between a process and a thread?

  1. Threads have their own private address space, while processes share one.
  2. Processes are always faster than threads because they are heavier.
  3. A thread can only exist without a process.
  4. A process has its own address space, while threads within a process share that address space. Correct answer.

Explanation

A process is an executing program with its own memory space and resources, whereas threads are units of execution inside a process that share its code, data and open files. Because threads share memory, communication between them is cheaper but requires synchronisation.

Question 42Software and Operating Systems

Two threads both increment a shared counter without any locking. What problem can occur?

  1. A page fault on every increment
  2. A race condition producing lost updates Correct answer.
  3. A deadlock caused by circular waiting
  4. A syntax error at compile time

Explanation

When two threads read, modify and write a shared variable without synchronisation, their operations can interleave so that one update overwrites the other, which is a race condition. Deadlock requires threads holding locks and waiting for each other, which is not the case here.

Question 43Software and Operating Systems

Which condition is necessary for a deadlock to occur among processes competing for resources?

  1. Use of a single process only
  2. Circular wait among the processes Correct answer.
  3. Preemption of every held resource
  4. Absence of any shared resource

Explanation

Deadlock requires four conditions to hold simultaneously, one of which is circular wait, where each process waits for a resource held by the next in a cycle. If the cycle can be broken, deadlock cannot persist.

Question 44Software and Operating Systems

What is thrashing in a virtual memory system?

  1. The kernel loads device drivers at boot time
  2. The disk is defragmented too frequently
  3. The CPU executes too many instructions per second
  4. The system spends most of its time swapping pages instead of executing processes Correct answer.

Explanation

Thrashing occurs when processes have too few frames for their working sets, so the system constantly faults pages in and out and useful CPU work collapses. The remedy is usually to reduce the degree of multiprogramming or allocate more frames.

Question 45Software and Operating Systems

Which access method allows a file to be read only in the order in which the records were written?

  1. Sequential access Correct answer.
  2. Random access
  3. Direct access
  4. Indexed access

Explanation

Sequential access requires records to be processed in their stored order, as with magnetic tape or a log file. Random or direct access allows records to be reached in any order, often using an index.

Question 46Software and Operating Systems

A user types a command into a command-line interpreter. Which component receives and executes it?

  1. The memory management unit
  2. The BIOS
  3. The disk controller
  4. The shell Correct answer.

Explanation

The shell is the command interpreter that reads user commands, interprets them and asks the kernel to perform the requested operations. The BIOS, memory management unit and disk controller are lower-level hardware or firmware components.

Question 47Software and Operating Systems

Which of the following is the main advantage of a microkernel architecture over a monolithic kernel?

  1. Easier isolation of services so a faulty driver is less likely to crash the whole system Correct answer.
  2. Removal of the need for any inter-process communication
  3. Fewer context switches for every system call
  4. Guaranteed faster disk throughput

Explanation

In a microkernel, most services such as drivers and file systems run as separate user-space processes communicating through message passing, so a failure in one service is contained. The trade-off is more inter-process communication and context switching overhead.

Question 48Software and Operating Systems

What does the term context switch mean in an operating system?

  1. Saving the state of one process and restoring the state of another so it can run Correct answer.
  2. Rebooting the computer after an update
  3. Changing the screen resolution of the display
  4. Converting a source file into an executable

Explanation

A context switch stores the registers and program counter of the current process in its process control block and loads the saved state of the next process. This lets the CPU resume a different process correctly, though it adds overhead.

Question 49Software and Operating Systems

Under the Banker's algorithm, a system is in a safe state when:

  1. All resources are held by a single process
  2. Every process has already terminated
  3. No process is currently waiting for any resource
  4. There exists at least one sequence in which all processes can complete without exceeding available resources Correct answer.

Explanation

A safe state means there is some ordering of processes such that each can obtain its maximum remaining claim from currently available plus released resources and finish. The algorithm grants a request only if the resulting state remains safe.

Question 50Software and Operating Systems

A paging system uses 32-bit virtual addresses and pages of 4 KB. How many bits of the virtual address form the page offset?

  1. 12 Correct answer.
  2. 22
  3. 20
  4. 10

Explanation

A 4 KB page contains 4096 bytes, and 2^12 = 4096, so 12 bits are needed to address a byte within a page. The remaining 20 bits identify the virtual page number.