Computer Hardware and System Architecture
This domain covers the physical parts of a computer and how they are wired together to run instructions. The exam tests whether you can name each component, state its function, and explain what happens during the fetch–decode–execute cycle.
Inside the system unit
- CPU: the ALU does arithmetic and logic; the control unit decodes instructions and coordinates the parts; registers hold the tiny amount of data in use right now (PC, MAR, MDR, CIR, accumulator).
- Buses: the address bus is one-way and carries addresses; the data bus is two-way and its width sets how many bits move per cycle; the control bus carries read/write, clock and interrupt signals.
- Memory hierarchy: registers → cache (L1/L2/L3) → RAM → secondary storage. Going down the list, capacity and access time rise while cost per byte falls.
- RAM is volatile (lost when power goes off); ROM is non-volatile and holds firmware such as the bootstrap loader. Cache is small, fast SRAM close to the CPU.
- Motherboard, expansion slots, power supply unit, ports, and peripherals (input, output, backing store).
Worked example
A processor has a 16-line address bus and one byte stored at each address. How much memory can it directly address? Each address line carries one bit, so the number of distinct addresses is 2^16 = 65 536. At one byte per address that is 65 536 bytes = 64 KiB. Reasoning: the address bus width fixes the maximum addressable capacity, while the data bus width fixes how many bits are fetched in one go.
Traps that cost marks
- Describing RAM as permanent storage, or cache as non-volatile.
- Confusing the two bus widths: address width = capacity, data width = transfer size.
- Claiming a higher clock speed alone guarantees a faster computer; cores, cache size and bus speed also count.
- Calling a hard disk "primary storage" - it is secondary/backing storage.