Hardware and computer architecture
Hardware and computer architecture examines the processor and the fetch–decode–execute cycle, the buses and registers that support it, the memory hierarchy, secondary storage and the trade-offs between RISC and CISC designs.
CPU components and registers
The control unit coordinates the cycle and decodes instructions; the ALU performs arithmetic and logic. The program counter (PC) holds the address of the next instruction, the memory address register (MAR) holds the address being accessed, the memory data register (MDR) holds the data or instruction transferred, the current instruction register (CIR) holds the instruction being executed, and the accumulator holds intermediate results. The address bus is one-way and carries addresses; the data bus is bidirectional; the control bus carries read/write and interrupt signals.
Fetch–decode–execute
Fetch: copy the PC to the MAR, signal a memory read, copy the word from MDR to CIR, increment the PC. Decode: the control unit splits the instruction into opcode and operand. Execute: the operation is carried out, registers or memory are updated, and flags are set.
Worked example
A processor has a 24-bit address bus and a 16-bit data bus. Addressable locations = 2^24 = 16,777,216. Each location holds 16 bits = 2 bytes, so total memory = 33,554,432 bytes = 32 MiB. The address bus, not the data bus, sets the number of locations.
Memory and storage
Cache is small, fast SRAM close to the CPU; virtual memory uses disk space when RAM is full and can cause thrashing. Magnetic storage is cheap per gigabyte with moving parts; solid-state storage has no moving parts, is faster and more shock-resistant but has limited write cycles; optical storage uses pits and lands read by laser.
RISC, CISC and pipelining
RISC uses simple fixed-length instructions and more registers; CISC uses fewer, more complex instructions. Pipelining overlaps stages of successive instructions, but hazards can stall it.
Traps
Confusing MAR and MDR; claiming the data bus determines addressable memory; saying cache is larger than RAM; ignoring the difference between a bus width in bits and bytes.