Hardware Safety and Reliability Engineering
Hardware safety and reliability engineering
This domain tests failure classification, reliability data, and the calculation that connects them to SIL. Expect λ, DC, SFF, HFT, PFDavg, proof-test interval, common cause, and architectural constraints.
Core rules
- Failures are safe or dangerous, detected or undetected. Only dangerous undetected failures (λDU) drive PFDavg in low demand.
- Diagnostic coverage DC = λDD/λD_total; safe failure fraction SFF = (λS + λDD)/λ_total. SFF and HFT constrain the achievable SIL in IEC 61508.
- For a 1oo1 element, PFDavg ≈ λDU × T/2, where T is the proof-test interval.
- Redundancy reduces random failure probability but raises common-cause vulnerability; apply a beta factor and verify independence.
- Reliability prediction supports SIL verification but does not replace proof testing, diagnostics, and configuration control.
Worked example
A 1oo1 pressure transmitter has λDU = 1.0e-6/h and a 12-month proof-test interval (8,760 h). PFDavg ≈ 1.0e-6 × 8,760/2 = 4.38e-3. That is within the SIL 2 band (1e-3 to 1e-2) for the sensor element. If the loop also includes a logic solver and valve, each element's PFDavg is added for a series architecture, and the total must meet the SIL 2 target. Reducing the proof-test interval to 6 months halves the sensor contribution.
Traps
- Using MTBF as if it were PFDavg.
- Counting detected failures as if they were undetected, which flatters the result.
- Ignoring the final element, often the largest contributor.
- Assuming redundancy alone achieves SIL without SFF, HFT, and common-cause checks.