TASC Electronics and Advanced Technologies Level 3 study plan

Compute series, parallel, and series-parallel equivalent resistance, capacitance, and inductance for mixed networks, showing each reduction step.

Apply Ohm's law, Kirchhoff's voltage and current laws, and the voltage divider rule to solve at least ten two-loop DC circuits by hand.

Calculate RC and RL time constants and sketch charge/discharge curves for step inputs, labeling the 63% and 5-time-constant points.

Explain the behavior of diodes, BJTs, and MOSFETs in one paragraph each, naming the terminals and the bias conditions for conduction.

Convert between peak, RMS, and average values for sinusoidal and half-wave rectified waveforms and state where each measure applies.

Design and calculate component values for inverting, non-inverting, and difference amplifier stages to hit specified gains within 5% tolerance.

Select and justify filter topologies (first- and second-order low-pass, high-pass) for a stated cutoff frequency and roll-off requirement.

Derive truth tables from a written logic specification and minimize the result with Karnaugh maps for three- and four-variable functions.

Convert minimized Boolean expressions into NAND-only and NOR-only gate implementations and verify equivalence algebraically.

Trace timing behavior of combinational versus clocked circuits, distinguishing setup, hold, and propagation delay effects on a stated design.

Compare microcontroller families on architecture, clock speed, memory, and peripheral set, and match three stated application requirements to suitable parts.

Write register-level descriptions of GPIO configuration, interrupt handling, and timer operation for one chosen microcontroller, without relying on library calls.

Map a peripheral set (ADC, PWM, UART, I2C, SPI) to the pins and registers needed for a specified embedded task.

Explain memory organization, stack behavior, and the difference between polling, interrupt, and DMA data paths in a written summary.

Draft a state machine for a small embedded function and translate it into pseudo-code with defined states, transitions, and timing constraints.

Configure ADC sampling parameters (resolution, reference, sample rate) for three stated measurement scenarios and compute resulting resolution in engineering units.

Classify ten given devices as sensors, actuators, or transducers and identify the physical quantity, output signal type, and typical interface circuit for each.

Design signal-conditioning paths (bridge, amplifier, filter, ADC) for a resistive sensor and a current-output sensor, calculating each stage's gain.

Select drive circuits for a DC motor, solenoid, and relay, justifying flyback protection and current-rating margins.

Calculate sensor resolution, sensitivity, and error budget contributions for a stated measurement chain.

Compare linear regulators and switching topologies (buck, boost, buck-boost) on efficiency, ripple, and complexity, and select one for each of three stated load profiles.

Calculate duty cycle, inductor value, and output ripple for a buck converter at given input, output, frequency, and load current.

Size a battery and specify charge-control approach for a stated runtime and load, including depth-of-discharge and derating assumptions.

Explain switching loss, conduction loss, and thermal path for a power device, and estimate junction temperature from a given thermal resistance chain.

Identify isolation, creepage, and inrush considerations that apply to a mains-connected power stage.

Compute bandwidth, signal-to-noise ratio, and Shannon capacity for given channel parameters and interpret each result in plain language.

Compare modulation schemes (ASK, FSK, PSK, QAM) on spectral efficiency and noise robustness, and choose one for two stated link requirements.

Describe the OSI and TCP/IP layer models and place ten named protocols at their correct layers with one-sentence roles.

Differentiate serial buses (UART, I2C, SPI, CAN, Ethernet) by topology, speed class, addressing, and typical application, and select one for each of three scenarios.

Identify addressing, subnetting, and error-detection basics by working through two subnetting examples and two checksum/CRC examples.

Classify systems as open-loop or closed-loop and derive transfer functions for first-order plants from given step-response data.

Determine stability and steady-state error for a stated loop using pole location and gain reasoning, and predict the effect of adding proportional versus integral action.

Tune a PID controller for a described process using a documented method and justify the chosen gains against overshoot and settling targets.

Select instruments (multimeter, oscilloscope, logic analyzer, current probe) for five measurement tasks and state the setting that most affects accuracy.

Apply a structured fault-isolation sequence (divide-and-conquer, signal tracing, substitution) to two written fault scenarios and document the decision tree.

Apply ESD, lockout/tagout, grounding, and PPE requirements to five described lab situations and identify the specific control that is missing in each.

Evaluate a design scenario against safety and compliance concerns (isolation, fusing, thermal limits, EMI) and list corrective actions in priority order.

Re-solve a mixed set of ten problems drawn from fundamentals and analog/digital design under timed conditions, targeting 80% or better.

Summarize the eight highest-error topics from all prior weeks into a single condensed review sheet with worked micro-examples.

Assemble a personal exam-day plan covering time allocation per domain weight and a check-and-verify routine for calculation questions.