Crosstalk and Return Path in a Mixed-Signal PCB
A 6-layer board carries a 14-bit, 10 MSPS ADC. Layer stack (top to bottom): signal, ground plane, signal, power plane, signal, ground plane. A 25 MHz SPI clock and a 100 MHz DDR interface run on layer 3, which is referenced to the power plane on layer 4. The analog front end on layer 1 is referenced to the solid ground plane on layer 2. The board fails radiated emissions at 300 MHz and 500 MHz by 4 dB. A ferrite bead separates analog and digital ground at a single point. The layout has one analog trace crossing a split in the ground plane beneath it, and the ADC's digital output bus changes layers through vias without stitching capacitors. The product must meet Class B limits with a 3 dB margin.
1. Explain why the layer-3 signals are a likely emissions source and why the single-point ground split makes it worse.
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Signals on layer 3 return through the layer-4 power plane. At 100 MHz and above, the return current follows the path of least impedance, which is directly under the trace in the plane. Any discontinuity - a plane split, a via, or a reference change - forces the return current to detour, creating a loop that radiates. The 300 MHz and 500 MHz failures are consistent with harmonics of the 100 MHz DDR clock and the 25 MHz SPI clock (12th and 20th harmonics; 300 MHz is the 12th of 25 MHz and the 3rd of 100 MHz). The single-point ferrite ground tie between analog and digital ground is the classic problem: at high frequency the ferrite is inductive, so the two grounds are effectively separated. Any signal crossing that boundary - and the analog trace crossing the split on layer 2 - has no continuous return path, so the return current flows in a large loop, radiating efficiently. The ferrite also creates a dipole antenna between the two ground planes. Modern mixed-signal design uses a single solid ground plane with careful partitioning of components, not a split.
2. Propose a prioritised set of layout and hardware fixes, and state how you would verify each.
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Priority 1: eliminate the analog trace crossing the ground split - reroute it so it stays entirely over solid ground on layer 2, or move the split. Verify with a near-field probe scan and a re-run of the radiated emissions test. Priority 2: replace the single-point ferrite ground tie with a solid ground plane; keep analog and digital components physically separated so their return currents do not share copper. Verify by measuring the ground plane impedance and checking that the ADC's noise floor does not degrade (measure SNR with a full-scale sine input before and after). Priority 3: add stitching capacitors (typically 100 nF plus 10 nF) between the layer-4 power plane and layer-2/6 ground near every via where a signal changes reference, and near the ADC digital outputs. Verify by checking the return-path continuity with a network analyser or by re-testing emissions. Priority 4: slow the DDR edge rates if timing allows (series resistors or drive-strength settings), which reduces high-frequency harmonic energy. Verify with an eye diagram and timing margin analysis. Priority 5: add a common-mode choke or ferrite on the offending cable if the emissions are cable-borne, verified by testing with and without the cable.
3. The team proposes adding a shielded enclosure to pass emissions. Assess this and state the risk.
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A shield can mask the symptom but does not fix the root cause. If the board radiates because of a large return-current loop, the loop is still there, and it will couple into cables leaving the enclosure, which then radiate outside the shield - the shield may not help at all if the cables are the antenna. Shielding also adds cost, weight, and assembly complexity, and it can create thermal and serviceability problems. The correct sequence is: fix the return paths first, re-measure, and only then consider shielding as a final margin measure. If shielding is used, cable entry must be filtered (feed-through capacitors or filtered connectors) and the shield must be bonded at multiple points to the chassis, otherwise the shield becomes a resonator. The 3 dB margin requirement means the design should be re-tested at worst-case temperature and with production-representative cables, not just a bench prototype.