AMIE Section B EEE Exam common mistakes
AMIE Section B EEE Exam · Understand the traps and how to avoid them.
Applying a single-phase loss formula (I²R) to a three-phase line without the 3× multiplier, or forgetting the √3 factor in three-phase power (P = √3·V_L·I_L·cosφ), so line losses and ratings come out wrong by a factor of 3 or √3.
Candidates memorise per-phase expressions and then substitute line voltage directly, losing track of whether the given voltage is phase or line value and whether the current is per-phase or line current.
What to do instead
Before substituting numbers, write the quantity definitions explicitly: mark V as line or phase, I as line or phase, and state the conversion used. For three-phase systems always start from total power S = √3·V_L·I_L and total loss = 3·I_phase²·R; check the answer dimensionally and numerically against a per-phase calculation done separately.
Treating a transformer or induction machine as ideal: ignoring magnetising current, core loss, slip, or copper loss when computing efficiency, regulation, or torque, and then reporting an efficiency of 100% or a rotor speed equal to synchronous speed.
Textbook formulas for ideal devices are easier to recall than the equivalent circuit, and candidates under time pressure skip the loss accounting entirely.
What to do instead
For every machine problem, draw the equivalent circuit and label the loss elements before computing. Use efficiency = output/(output + copper loss + core loss + mechanical loss), and for induction machines always compute slip s = (n_s − n_r)/n_s and rotor frequency f_r = s·f. Sanity-check that efficiency is below 100% and rotor speed is below synchronous speed.
Confusing real, reactive and apparent power, or mixing up the leading/lagging power-factor correction direction, so a capacitor bank is sized to the wrong kVAR or the power factor is reported as improved when it has actually worsened.
The three power quantities share the same units in casual speech, and candidates apply the correction formula without tracking the sign of the reactive component.
What to do instead
Always tabulate P, Q and S with units (W, var, VA) and sketch the power triangle before and after correction. Size capacitors from Q_c = P(tanφ₁ − tanφ₂) and state explicitly that capacitors supply lagging reactive power, so they correct a lagging load. Verify that S decreases and cosφ increases after correction.
Designing a combinational or sequential circuit without a complete truth table or state diagram, then failing to minimise, leaving hazards, or producing a state machine whose unused states are unhandled and whose outputs are wrong on the first clock edge.
Candidates jump straight to a gate-level sketch from the verbal specification, skipping the systematic truth-table/state-table step that exposes don't-care conditions and illegal states.
What to do instead
Always build the full truth table or state table first, derive minimised expressions with Karnaugh maps or Boolean algebra, and for sequential designs assign and document state codes, then add a reset and check unused-state recovery. Simulate or hand-trace the clocked behaviour for at least two cycles before finalising.
Ignoring the transmission-line and impedance-matching regime: applying low-frequency lumped-circuit reasoning to a line whose length is a significant fraction of a wavelength, or mismatching source and load impedances and then wondering why reflected power or standing waves appear.
Candidates treat all interconnects as ideal wires and do not check the electrical length or the impedance relationship before choosing a model.
What to do instead
First compute electrical length (length/wavelength) and compare line length with wavelength; if it is not electrically short, use distributed models (characteristic impedance, propagation constant, reflection coefficient). For matching, verify Z_load = Z_source* (or the specified conjugate match), compute Γ and VSWR to confirm the result, and state the frequency at which the match holds.
Confusing analogue modulation parameters: quoting bandwidth or sideband positions for AM/FM without applying Carson's rule or the correct modulation index, or mixing up SNR improvement from FM with the threshold effect.
AM and FM formulas look similar and candidates recall the general shape of the expression but not the factor of 2 or the dependence on modulation index.
What to do instead
Write the modulated signal expression explicitly before computing. For AM, bandwidth is 2f_m and sidebands sit at f_c ± f_m; for FM, use Carson's rule B ≈ 2(Δf + f_m) and state the modulation index β = Δf/f_m. Check whether the question asks for bandwidth, deviation, or power in sidebands, and confirm units in Hz.
Analysing an algorithm by its outer loop only, quoting O(n) for nested loops or ignoring the cost of library operations (sorting, string concatenation, hash collisions), so the complexity and running-time estimates are wrong.
Candidates count loops visually rather than reasoning about how many times the innermost operation executes as a function of input size, and they treat built-in calls as free.
What to do instead
Derive complexity from the innermost statement: sum the number of executions over all loop levels and express it in terms of n, then drop constants and lower-order terms. Account for the documented cost of library calls (for example comparison sorting is O(n log n)), consider best/average/worst cases separately, and verify with small n by counting operations manually.
Describing a database or process design without normalisation or concurrency reasoning: proposing tables that repeat data, or a schedule that is not serialisable, and then claiming correctness because the sample data happens to work.
Candidates validate designs against a single example rather than against functional dependencies and interleaved transactions, so anomalies only appear with other data or concurrent access.
What to do instead
List functional dependencies and check each table against 1NF, 2NF and 3NF (or state a justified denormalisation). For concurrency, test the schedule with a serialisability check (precedence graph or two-phase locking argument), and state isolation level and locking assumptions explicitly. Test the schema against at least one insert, update and delete anomaly scenario.
Selecting a beam or shaft section by checking only bending stress and omitting transverse shear, deflection, or combined-stress (principal stress) checks, so the chosen section passes on paper but fails the actual design criteria.
Candidates anchor on the first formula they recall (σ = My/I) and stop, forgetting that the problem statement may impose a deflection limit or that shear and bending act together at the same point.
What to do instead
Enumerate every limit state required by the problem (bending, shear, deflection, buckling, fatigue) and check each one with its own criterion before concluding. For combined loading, compute principal stresses or use an appropriate failure theory (von Mises or Tresca) and compare against the allowable. Report the governing case explicitly.
Using a factor of safety or load combination without stating the code basis, or mixing allowable-stress and limit-state (LRFD/partial-factor) methods in the same calculation, producing an unsafe or inconsistent result.
Candidates blend remembered load factors with service loads because both methods appear in coursework, and they omit the load combination that actually governs.
What to do instead
State the design method at the start (allowable stress or limit state) and apply only that method's factors throughout. Write out each relevant load combination, evaluate all of them, and identify the governing one. Keep service loads and factored loads in separate columns so the units and factors cannot be mixed, and cite the code clause or design assumption behind each factor.