Ruankao Embedded System Designer (Intermediate) cheat sheet

State whether addresses refer to bytes or words before calculating capacity.

Distinguish PC, instruction register, address register and data register.

For n-bit two’s complement the range is−2^(n−1) through 2^(n−1)−1.

Cache locality and pipeline hazards matter more than a clock-rate label alone.

Use the actual memory map, register semantics and addressable unit.

Voltage compatibility and current-drive capability are separate checks.

State ADC endpoint and timing conventions before calculating.

Volatile is not a concurrency lock or an atomicity guarantee.

Judge timing under stated deadlines and worst-case assumptions.

Priority inversion and shared-state ownership need actual protocols.

A successful host build does not establish target timing or memory behavior.

Authenticated firmware still needs compatibility, functional tests and recovery design.

Draw a scheduling timeline before averaging waits.

Distinguish a TLB miss from a nonresident page fault.

LRU is a stack algorithm; FIFO can exhibit Belady’s anomaly.

Protect the shared invariant and analyze actual wait dependencies.

Recursion needs a base case and progress toward that base case.

Overloading uses different signatures; overriding replaces an inherited method.

Unit tests isolate units; integration tests combine them.

Short-circuit evaluation can skip the right operand.

Pass-by-value copies arguments; pass-by-reference can mutate the caller's object.

Decomposition breaks problems down; abstraction removes irrelevant detail.

Binary search requires sorted data and is O(log n).

Merge sort is O(n log n) worst case; bubble sort is O(n^2).

Trace tables prevent guessing about loop output.

Update search bounds to mid + 1 or mid - 1, not mid.

Trace observable quality criteria to design and verification evidence.

DFD, ER and UML views answer different questions.

Choose architectural styles from constraints, not product fashion.

Separate verification against specification from validation for actual use.

Link security requirements and threat modeling to real design choices.

Use server-side enforcement and interpreter/context-appropriate defenses.

Static, dynamic and dependency analysis provide different evidence.

Protect and trace source, builds, dependencies and release artifacts.

CIA triad plus authenticity, non-repudiation and accountability define what is protected.

Risk combines threat, vulnerability and business impact; a vulnerability alone is not a risk.

Bell-LaPadula: no read up, no write down - confidentiality.

Biba: no read down, no write up - integrity.

Governance decides acceptable risk and accountability; management decides how to achieve it

Risk appetite (board-approved) differs from tolerance (variation) and capacity (maximum bearable)

Three Lines Model: internal audit must remain independent of control ownership