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Ruankao Embedded System Designer (Intermediate) study materials
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Ruankao Embedded System Designer (Intermediate) practice questions

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Question 1Computer architecture, logic and data representation

What is the unsigned decimal value of the 8-bit binary pattern 11010110?

  1. 182
  2. 198
  3. 214 Correct answer.
  4. 246

Explanation

Unsigned 11010110 equals 128+64+16+4+2 = 214. Each 1 contributes its place value: 2^7, 2^6, 2^4, 2^2, and 2^1. 软考 基础知识 items routinely ask this conversion without a calculator.

Question 2Computer architecture, logic and data representation

Convert hexadecimal 0x2A to decimal.

  1. 26
  2. 42 Correct answer.
  3. 52
  4. 162

Explanation

Hexadecimal 0x2A is 2×16 + 10 = 42 because A is ten. The same value is binary 00101010. Mixing hex digit values with decimal place weights is a common 软考 trap.

Question 3Computer architecture, logic and data representation

Which 8-bit two's-complement encoding represents decimal −13?

  1. 00001101
  2. 10001101
  3. 11110010
  4. 11110011 Correct answer.

Explanation

Write +13 as 00001101, invert the bits to 11110010 (one's complement), then add 1 to obtain 11110011. Sign-magnitude 10001101 and the inverted pattern without the +1 are the usual distractors on 软考 numeric items.

Question 4Computer architecture, logic and data representation

What is the representable range of 8-bit two's-complement integers?

  1. −128 to +127 Correct answer.
  2. −127 to +127
  3. −128 to +128
  4. 0 to 255

Explanation

In n-bit two's complement the range is −2^(n−1) through +2^(n−1)−1. For n=8 that is −128 to +127. There is one more negative value than positive because 10000000 is −128 and has no positive counterpart.

Question 5Computer architecture, logic and data representation

A processor uses a perfectly balanced 5-stage pipeline with no hazards or stalls. How many clock cycles does it take to complete 100 instructions, assuming one instruction enters the pipeline per cycle after fill?

  1. 100
  2. 104 Correct answer.
  3. 500
  4. 20

Explanation

The first instruction occupies 5 cycles (fill). Each of the remaining 99 instructions completes one cycle later, so total cycles = 5 + 99 = 104, equivalently k+(n−1) for k stages and n instructions. Non-pipelined execution would take 100×5 = 500 cycles.

Question 6Computer architecture, logic and data representation

An even-parity bit is appended to the 7-bit data 1011011. What is the parity bit?

  1. 0
  2. 1 Correct answer.
  3. X (don't care)
  4. The MSB of the data

Explanation

Even parity makes the total number of 1s even, including the parity bit. 1011011 has five 1s (odd), so the parity bit must be 1 to make six 1s. Odd count of 1s in the data is the cue to set even-parity to 1.

Question 7Computer architecture, logic and data representation

A firmware designer must move 4096 ADC samples from a peripheral FIFO into SRAM with the least CPU involvement per sample. Which I/O control method is the best fit?

  1. DMA (direct memory access) Correct answer.
  2. Programmed I/O polling in a tight CPU loop
  3. Memory-mapped register reads from the main thread only
  4. Interrupt-driven transfer of one sample per ISR with no DMA

Explanation

DMA lets a controller transfer blocks between a peripheral and memory after the CPU programs source, destination, and count. Polling and per-sample ISRs keep the CPU in the path for every word. Memory-mapped I/O is how the registers are addressed, not a bulk-offload method by itself.

Question 8Computer architecture, logic and data representation

After a cache miss on address 0x2000, the next sequential instruction fetch at 0x2004 hits. Which locality property is this primarily illustrating?

  1. Temporal locality only
  2. Write-back allocation
  3. Compulsory-miss elimination by associativity
  4. Spatial locality Correct answer.

Explanation

Spatial locality is the tendency to access addresses near a recent access. A cache line fill brings a block of neighboring words, so 0x2004 can hit after 0x2000 missed. Temporal locality is reuse of the same address over time, which this stem does not show.

Question 9Computer architecture, logic and data representation

A 16 KiB direct-mapped cache has 32-byte lines. How many bits are used for the line offset and the index (set) field of a byte address?

  1. Offset 4 bits, index 8 bits
  2. Offset 5 bits, index 9 bits Correct answer.
  3. Offset 5 bits, index 10 bits
  4. Offset 6 bits, index 8 bits

Explanation

Line size 32 bytes ⇒ offset = log2(32) = 5 bits. Number of lines = 16 KiB / 32 B = 16384/32 = 512, so index = log2(512) = 9 bits. Direct-mapped means one line per set, so sets equal lines.

Question 10Computer architecture, logic and data representation

In synchronous digital design, how does a positive-edge-triggered D flip-flop differ from a level-sensitive D latch?

  1. The flip-flop samples D continuously while CLK is high; the latch samples only on the rising edge
  2. Both sample D only on the falling edge of CLK
  3. The flip-flop captures D at the rising clock edge; the latch is transparent while the enable is active Correct answer.
  4. The latch stores two bits; the flip-flop stores one

Explanation

A D latch is transparent for the whole time its enable (often CLK) is at the active level, so D can race through. An edge-triggered D flip-flop samples D only at the clock edge, which is why sequential timing analysis uses setup and hold around that edge.

Question 11Computer architecture, logic and data representation

Setup time (tsu) of a flip-flop is best described as:

  1. The time D must remain stable before the capturing clock edge Correct answer.
  2. The time D must remain stable after the capturing clock edge
  3. The CLK-to-Q contamination delay only
  4. The minimum allowed clock-low pulse width

Explanation

Setup time is the interval before the active edge during which D must already be stable. Hold time is the interval after the edge. CLK-to-Q is an output delay, and pulse-width limits are separate datasheet constraints.

Question 12Computer architecture, logic and data representation

Two independent modules are placed in series so the system works only if both work. If their reliabilities are 0.90 and 0.95, what is the system reliability?

  1. 0.99
  2. 1.85
  3. 0.95
  4. 0.855 Correct answer.

Explanation

Series reliability multiplies: R = 0.90 × 0.95 = 0.855. Parallel redundant reliability would be 1−(1−R1)(1−R2), which is larger than either module, not smaller. Adding reliabilities is not a valid model.

Question 13Computer architecture, logic and data representation

For binary codes, what is the minimum Hamming distance required to correct any single-bit error?

  1. 1
  2. 3 Correct answer.
  3. 2
  4. 5

Explanation

To correct t-bit errors the minimum distance must satisfy d_min ≥ 2t+1. For t=1, d_min ≥ 3. Distance 2 can detect a single error but cannot always tell which codeword was sent. Distance 1 cannot even detect a single flip.

Question 14Computer architecture, logic and data representation

Which statement best matches a RISC load/store architecture used in many embedded MCUs?

  1. Only load and store instructions access memory; ALU operations use registers Correct answer.
  2. Every ALU instruction can take one operand from memory
  3. Microcode implements each instruction as many internal steps by design
  4. The instruction set is defined to maximize instruction encoding density at any cost to pipeline regularity

Explanation

Classic RISC (ARM included) uses a load/store model: memory is accessed by dedicated loads/stores, and arithmetic uses registers. CISC encodings often allow memory operands in ALU ops. Microcode and density-at-all-costs describe CISC trade-offs, not the RISC principle.

Question 15Computer architecture, logic and data representation

A microcontroller has separate buses and memories for instructions and data so that a fetch and a data access can occur in the same cycle. Which organization is this?

  1. Von Neumann (Princeton) architecture
  2. Stack architecture with a single TOS bus
  3. Harvard architecture Correct answer.
  4. SISD with a unified cache only

Explanation

Harvard architecture separates instruction and data paths (and typically memories), enabling simultaneous fetch and data access. Von Neumann uses a single shared memory/bus, so instruction fetch and data access contend. Many Cortex-M parts present a modified Harvard system with separate I/D buses to a shared memory controller.

Question 16Embedded hardware, interfaces and timing assumptions

Compared with DRAM, which property is characteristic of SRAM used as on-chip MCU RAM?

  1. It must be refreshed periodically or stored bits decay
  2. It does not require refresh and is typically faster but less dense Correct answer.
  3. It is always used as the only off-chip mass storage
  4. It stores data as charge on a capacitor per cell

Explanation

SRAM cells are bistable (typically 6T) and hold data without refresh; they are fast and used as on-chip RAM and caches. DRAM uses a capacitor that needs refresh and is denser and cheaper per bit for large off-chip memory. Confusing the two is a staple 软考 memory-classification item.

Question 17Embedded hardware, interfaces and timing assumptions

A designer wants to execute firmware in place from non-volatile memory without first copying the image to RAM. Which flash type is the usual choice?

  1. NOR flash (execute-in-place capable random read) Correct answer.
  2. NAND flash without a RAM shadow
  3. DRAM only
  4. EEPROM page mode exclusively

Explanation

NOR flash supports random reads at addresses suitable for a CPU fetch, so execute-in-place (XIP) is common. NAND is organized in pages/blocks with bad-block handling and is used for bulk storage, typically with code copied to RAM. DRAM is volatile. EEPROM is for small parameter storage, not a full XIP code image in most MCUs.

Question 18Embedded hardware, interfaces and timing assumptions

ARM Cortex-M3/M4 class microcontrollers typically provide which memory-protection facility, as opposed to a full virtual-memory MMU?

  1. A stage-2 hypervisor MMU only
  2. An x86-style paging MMU with TLBs required for all C code
  3. A TrustZone-A EL2 MMU as the only option
  4. An MPU (memory protection unit) that regions physical addresses without virtual paging Correct answer.

Explanation

Cortex-M profiles used in MCUs provide an optional MPU: region-based access control on physical addresses, without a translation lookaside buffer or virtual paging. A full MMU (virtual memory) is characteristic of Cortex-A application processors. 软考 hardware items contrast MCU versus MPU/MMU roles.

Question 19Embedded hardware, interfaces and timing assumptions

On ARM Cortex-M, which on-chip block nests and prioritizes peripheral interrupts and vectors the CPU to the matching handler?

  1. The system MPU exclusively
  2. The debug SWD-DP only
  3. The NVIC (Nested Vectored Interrupt Controller) Correct answer.
  4. The SysTick timer by itself

Explanation

The NVIC is the Cortex-M interrupt controller: it prioritizes IRQs, supports nesting, and provides vectored entry to handlers. SysTick is one exception source. The MPU protects regions; SWD-DP is a debug port. These names are standard ARM-M teaching vocabulary.

Question 20Embedded hardware, interfaces and timing assumptions

UART (asynchronous serial) communication between an MCU and a PC typically requires which clock arrangement?

  1. A shared dedicated clock wire like SPI SCK
  2. Independent baud-rate clocks on each side, plus start/stop framing, with no shared clock line Correct answer.
  3. I2C-style open-drain SCL generated by the slave only
  4. CAN-style recessive/dominant arbitration on TX

Explanation

UART is asynchronous: each side uses its own baud-rate generator; a start bit aligns sampling. There is no shared clock pin (unlike SPI). I2C uses SCL and open-drain addressing; CAN is a multi-master differential bus with ID arbitration - different protocols.

Question 21Embedded hardware, interfaces and timing assumptions

Which statement correctly characterizes SPI relative to I2C for MCU peripherals?

  1. SPI is typically full-duplex with a separate clock and chip-select, often using four wires (SCLK, MOSI, MISO, SS) Correct answer.
  2. SPI always uses 7-bit slave addresses on a two-wire open-drain bus
  3. SPI requires differential signaling and bitwise ID arbitration
  4. SPI cannot exceed a few kilobits per second by protocol definition

Explanation

SPI is a synchronous master/slave bus: SCLK plus MOSI/MISO enable full-duplex, and SS selects a slave. I2C is the two-wire addressed open-drain bus. CAN is the differential multi-master bus. SPI clock rates commonly reach tens of MHz, so a few-kbps ceiling is false.

Question 22Embedded hardware, interfaces and timing assumptions

Why do I2C SDA and SCL lines normally need pull-up resistors?

  1. Because I2C drivers are always push-pull and the pull-ups speed the falling edge
  2. Because I2C is a current-loop interface like MIDI
  3. Because CAN transceivers require a 120 Ω pull-up to 5 V on each pin
  4. Because devices drive the bus open-drain/open-collector and can only pull the line low; the resistor restores logic 1 Correct answer.

Explanation

I2C uses wired-AND open-drain drivers: any device may pull the line low; none drive high. External (or internal) pull-ups return the line to VCC for logic 1 and allow multi-master without driver fights. Push-pull SPI lines do not need this wired-AND arrangement.

Question 23Embedded hardware, interfaces and timing assumptions

On a CAN bus, which mechanism lets the highest-priority frame win when two nodes start transmitting?

  1. Token passing from a dedicated master
  2. Non-destructive bitwise arbitration using the CAN identifier (dominant 0 overrides recessive 1) Correct answer.
  3. CSMA/CD jamming and random backoff as on classic Ethernet
  4. I2C ACK clock stretching

Explanation

CAN uses CSMA/CR: while sending the identifier, a node that transmitted recessive but reads dominant loses and becomes a receiver. A lower numeric ID (more leading dominant bits) wins. That is not Ethernet collision jamming, not a token ring, and not I2C ACK.

Question 24Embedded hardware, interfaces and timing assumptions

A 12-bit ADC uses Vref = 3.3 V and ideal coding V = code × Vref / 2^12. Which value is closest to one LSB?

  1. 3.3 mV
  2. 12 mV
  3. 0.806 mV Correct answer.
  4. 0.80 V

Explanation

2^12 = 4096, so LSB = 3.3 / 4096 ≈ 0.0008057 V ≈ 0.806 mV. 3.3 mV would be 3.3/1000; 0.80 V is nearly a quarter of full scale. 软考 hardware papers expect this division, not a datasheet lookup.

Question 25Embedded hardware, interfaces and timing assumptions

PWM duty cycle used to dim an LED from an MCU timer is defined as:

  1. The ratio of high (on) time to the PWM period Correct answer.
  2. The timer clock frequency divided by 2 only
  3. The ADC resolution in bits
  4. The UART baud rate

Explanation

Duty cycle = t_on / T_period (often expressed as a percentage). Average voltage (and perceived brightness with a filter) scales with duty. It is not the timer clock/2, not ADC bits, and not a serial baud rate.

Question 26Embedded hardware, interfaces and timing assumptions

What is the intended effect if firmware stops servicing (kicking) a watchdog timer before it expires?

  1. The MCU continues forever in the same hung loop with no reset
  2. Flash is guaranteed to be erased
  3. The watchdog typically asserts a reset (or NMI, if so configured) to recover the system Correct answer.
  4. All DMA channels are paused until the next UART interrupt

Explanation

A watchdog is a hardware timer that resets (or otherwise interrupts) the MCU if not cleared in time, recovering from software hangs. It does not erase flash by itself and does not pause DMA as its primary purpose. Failing to kick it is supposed to cause recovery, not silent continuation.

Question 27Embedded hardware, interfaces and timing assumptions

DMA is used in an embedded ADC logger primarily to:

  1. Replace the need for any clock tree
  2. Transfer sample blocks to memory with minimal per-sample CPU intervention Correct answer.
  3. Perform floating-point FFT in hardware on all Cortex-M0 parts
  4. Generate I2C addresses automatically

Explanation

DMA moves data between peripherals and memory after setup, which is why high-rate ADC logging uses it. It does not replace the clock tree, does not imply an FFT engine on every M0, and does not generate I2C addresses.

Question 28Embedded hardware, interfaces and timing assumptions

An STM32-style timer is clocked at 8 MHz with PSC = 7999 and ARR = 999 (both register values). What is the counter overflow frequency, using overflow = f_clk / ((PSC+1)×(ARR+1))?

  1. 8 kHz
  2. 8 MHz
  3. 1 kHz
  4. 1 Hz Correct answer.

Explanation

(PSC+1) = 8000 and (ARR+1) = 1000, so the divider is 8,000,000. Overflow frequency = 8×10^6 / 8×10^6 = 1 Hz (one overflow per second). Forgetting the +1 on PSC/ARR is the usual wrong path to 8 kHz or 1 kHz.

Question 29Embedded hardware, interfaces and timing assumptions

In AMBA-based MCU interconnects, which bus is typically the lower-bandwidth, lower-power peripheral bus versus the high-performance system bus?

  1. APB (Advanced Peripheral Bus) Correct answer.
  2. AHB as the only slow UART bus
  3. PCIe root complex
  4. USB OTG as the CPU instruction bus

Explanation

AMBA APB is designed for low-bandwidth peripherals (simple, low power). AHB (and later AXI) carries higher-performance system traffic. PCIe and USB are chip-to-chip/device interconnects, not the on-chip CPU-to-APB bridge role in a typical MCU.

Question 30Embedded hardware, interfaces and timing assumptions

An MCU GPIO input is left floating (not driven by a switch). Which practice avoids undefined logic levels?

  1. Leave the pin analog-only with no bias on a digital input
  2. Drive the pin as a high-speed SPI clock instead
  3. Enable an internal or external pull-up or pull-down (or keep the pin in a defined analog mode) Correct answer.
  4. Connect the pin directly to both VCC and GND

Explanation

A floating CMOS input can sit near threshold, causing oscillation and extra current. Pull-up/pull-down resistors (internal or external) define the idle level. Tying a pin to both rails shorts the supplies. Switching it to SPI does not fix an unused input.

Question 31Embedded hardware, interfaces and timing assumptions

ARM Cortex-M processors in the usual MCU configuration store a 32-bit word with which endianness by default?

  1. Big-endian only, with the most significant byte at the lowest address
  2. Little-endian by default: the least significant byte at the lowest address Correct answer.
  3. PDP-endian mixed byte order required by the architecture
  4. Endianness is undefined and randomly chosen at each reset

Explanation

The ARM Cortex-M programmers' model is little-endian by default: the least significant byte of a word sits at the lowest address. Some parts can be configured for big-endian data, but teaching and 软考 items treat little-endian as the MCU default. Endianness is not random at reset.

Question 32Embedded hardware, interfaces and timing assumptions

A 10-bit ADC uses Vref = 5.0 V and V = code × Vref / 2^10. What voltage corresponds to code 512?

  1. 2.5 V Correct answer.
  2. 5.0 V
  3. 1.25 V
  4. 0.512 V

Explanation

2^10 = 1024, so 512/1024 × 5.0 V = 2.5 V (half of full scale). Code 1023 is near 5 V, not 512. 0.512 V confuses the code with volts.

Question 33Embedded hardware, interfaces and timing assumptions

The Thumb-2 instruction set used on Cortex-M3/M4 is best described as:

  1. Only 8-bit PIC-style opcodes
  2. Only 64-bit AArch64 application instructions
  3. Only 32-bit ARM instructions with no 16-bit encodings
  4. A mix of 16-bit and 32-bit Thumb encodings for density and performance Correct answer.

Explanation

Thumb-2 blends 16-bit and 32-bit Thumb instructions so Cortex-M cores get better code density than ARM-only 32-bit encodings while still having 32-bit ops for richer operations. It is not 8-bit PIC, not AArch64, and not ARM-state-only 32-bit.

Question 34Embedded hardware, interfaces and timing assumptions

Immediately after a power-on reset, a typical Cortex-M MCU fetches the initial stack pointer and reset handler from which location?

  1. A random SRAM address
  2. The vector table at the start of mapped code flash (or remapped boot alias), beginning with SP and Reset_Handler Correct answer.
  3. The last address of SRAM only
  4. The I2C address 0x50

Explanation

Cortex-M reset reads word 0 as the main stack pointer and word 1 as the reset vector from the vector table, normally at the start of flash (address 0 or a boot remapping). SRAM contents are undefined until initialized. I2C addresses are unrelated to CPU reset fetch.

Question 35Embedded hardware, interfaces and timing assumptions

Bit-banding on Cortex-M3/M4 provides which software benefit for a GPIO or SRAM bit?

  1. It doubles the CPU clock automatically
  2. It translates every load into an I2C transaction
  3. A word access in the bit-band alias region reads or writes a single bit atomically without a read-modify-write of the whole peripheral register Correct answer.
  4. It disables the NVIC

Explanation

Bit-band aliases map each bit of a region to a word address: writing 1/0 to that word sets/clears the bit. That avoids a non-atomic read-modify-write race on a shared register. It does not change the CPU clock, talk I2C, or disable the NVIC. (Cortex-M0 typically lacks bit-banding.)

Question 36Embedded hardware, interfaces and timing assumptions

For a multi-drop industrial link of several nodes over tens of meters, which UART-related physical layer is the usual choice versus RS-232?

  1. RS-485 (differential, multi-drop capable) Correct answer.
  2. TTL-level TX/RX on a 20 m unshielded pair with no transceiver
  3. USB device only
  4. Single-ended RS-232 to 15 nodes without converters

Explanation

RS-485 uses differential signaling and supports multi-drop buses over longer cables. RS-232 is single-ended, point-to-point, and short-range. Bare TTL UART pins are not a long multi-drop industrial PHY. USB is a different tree-structured protocol.

Question 37Embedded hardware, interfaces and timing assumptions

An analog sensor bandwidth of interest is 200 Hz. According to the Nyquist sampling theorem, the ADC sample rate must be greater than which value, and what analog block is placed before the ADC to limit higher frequencies?

  1. 100 Hz, with a high-pass differentiator only
  2. 400 Hz, with an anti-aliasing low-pass filter Correct answer.
  3. 200 kHz, with no filter needed
  4. 1 Hz, with a PLL

Explanation

Nyquist requires fs > 2×fmax, so fs > 400 Hz for a 200 Hz band. Frequencies above Nyquist alias into the baseband, so an analog low-pass (anti-aliasing) filter is used before sampling. Sampling at 100 Hz would alias 200 Hz content. A PLL is not the anti-alias filter.

Question 38Real-time scheduling, firmware lifecycle and dependable state

Why must a C variable that is shared with an ISR, or that maps a hardware register, usually be declared volatile?

  1. So the compiler will not optimize away or cache loads/stores that the program text appears not to need Correct answer.
  2. So the linker places it in flash only
  3. So the CPU raises a usage fault on every access
  4. So printf becomes async-signal-safe

Explanation

volatile tells the compiler that every access has a side effect visible outside the current translation (hardware or another context). Without it, a loop waiting on a flag may read a register once into a CPU register and never see the ISR update. volatile does not make a variable atomic or ISR-safe by itself, and it is not a flash or fault attribute.

Question 39Real-time scheduling, firmware lifecycle and dependable state

Cross-compilation for an MCU project means:

  1. Compiling and running the firmware on the same Cortex-M chip that will ship
  2. Using a Java JIT on the target as the only build step
  3. Building on a host (for example x86) with a toolchain that emits code for a different target (for example ARM Cortex-M) Correct answer.
  4. Assembling by hand without a linker

Explanation

A cross-compiler runs on the development host and generates objects for another architecture. Embedded work almost always cross-compiles (arm-none-eabi-gcc and similar). Compiling on the target is native compilation. A JIT or hand assembly is not the definition.

Question 40Real-time scheduling, firmware lifecycle and dependable state

At C startup on a typical MCU, what is done with the .data and .bss sections before main()?

  1. .data is discarded; .bss is loaded from a UART
  2. .data initializers are copied from flash into RAM; .bss is zero-filled in RAM Correct answer.
  3. Both remain uninitialized in flash only
  4. The compiler forbids both sections in embedded C

Explanation

Initialized globals (.data) have a load-time image in flash that startup code copies into RAM. Uninitialized globals (.bss) have no flash image and are zeroed in RAM. That is why changing a global initializer grows the flash image, while a BSS global grows RAM only.

Question 41Real-time scheduling, firmware lifecycle and dependable state

Which practice is appropriate for a typical MCU interrupt service routine?

  1. Call malloc and printf freely to log every event
  2. Wait on a mutex that another task may hold for seconds
  3. Run a several-hundred-millisecond blocking state machine inside the ISR
  4. Keep the ISR short: clear the source, copy needed data, and defer work to a task (or a FromISR-safe RTOS primitive) Correct answer.

Explanation

ISRs run at interrupt priority, block lower-priority work, and often cannot block on locks or use non-reentrant libraries. The standard pattern is acknowledge, capture, signal a task. malloc/printf and mutex waits are classic hang or deadlock causes.

Question 42Real-time scheduling, firmware lifecycle and dependable state

In a preemptive priority RTOS, when a high-priority task becomes ready while a lower-priority task is running, what happens (assuming preemption is enabled)?

  1. The high-priority task preempts and runs; the lower-priority task is switched out Correct answer.
  2. The lower-priority task always runs to completion first
  3. Tasks always round-robin regardless of priority
  4. The scheduler waits for the next UART idle interrupt only

Explanation

Preemptive priority scheduling means a newly ready higher-priority task interrupts the current lower-priority task. Cooperative scheduling would wait for a yield. Equal-priority round-robin is a separate policy, not a replacement for priority preemption.

Question 43Real-time scheduling, firmware lifecycle and dependable state

When should firmware use a mutex rather than a binary semaphore to protect a shared SPI bus?

  1. When the goal is only to signal an ISR that a byte arrived, with no owner
  2. When counting a pool of 10 identical DMA buffers
  3. When a task must lock, possibly nest or inherit priority, and only the owner should unlock the bus Correct answer.
  4. When broadcasting an event bit to many waiters without exclusion

Explanation

A mutex has an owner, is used for mutual exclusion, and on many RTOSes supports priority inheritance to limit inversion. A binary semaphore is for signaling (give from ISR, take in task) and usually should not be used as a recursive lock. Counting semaphores track resource counts. Event flags broadcast bits.

Question 44Real-time scheduling, firmware lifecycle and dependable state

Task H needs a mutex held by low-priority task L, while medium-priority task M runs and prevents L from running. What is this, and which mutex feature is designed to reduce it?

  1. Deadlock; disable all interrupts forever
  2. Priority inversion; priority inheritance (L temporarily runs at H's priority while holding the mutex) Correct answer.
  3. Stack overflow; enlarge M's stack only
  4. Priority inversion; always make M higher than H

Explanation

Priority inversion is H blocked on a lock owned by L while M (in between) monopolizes the CPU. Priority inheritance boosts L to H's priority so L can finish and release. Raising M above H would make inversion worse. Disabling interrupts forever is not a mutex protocol. Stack size is a different defect.

Question 45Real-time scheduling, firmware lifecycle and dependable state

Two RTOS tasks must exchange variable-length sensor records without sharing a global buffer they both mutate. Which primitive is the usual fit?

  1. A message queue (or mailbox) that copies or references queued items Correct answer.
  2. A mutex with no data path
  3. Busy-waiting on a GPIO pin
  4. Stopping the scheduler permanently

Explanation

Message queues (and mailboxes) pass data or pointers between tasks with blocking/timeout semantics. A mutex only serializes; it does not queue records. GPIO polling and stopping the scheduler are not the communication pattern.

Question 46Real-time scheduling, firmware lifecycle and dependable state

A driver manages a pool of 4 identical DMA descriptors. Which RTOS object typically tracks how many are free?

  1. A mutex used as a binary lock only
  2. An event flag that stores Ethernet frames
  3. The NVIC pending register
  4. A counting semaphore initialized to 4 Correct answer.

Explanation

A counting semaphore's count represents available instances of a resource. Initialize to 4, take before allocating a descriptor, give when freeing. A mutex is one-at-a-time ownership of a single object, not a count of 4. Event flags and NVIC pending bits are not resource pools.

Question 47Real-time scheduling, firmware lifecycle and dependable state

On Cortex-M with a typical RTOS (for example FreeRTOS), why is PendSV often used for context switching rather than switching inside every ISR?

  1. PendSV is a debug-only exception unused at run time
  2. PendSV raises NMI which cannot be masked
  3. PendSV can be pending at the lowest exception priority so switch happens after nested ISRs unwind, using a dedicated handler Correct answer.
  4. PendSV replaces the need for a main stack pointer

Explanation

ISRs should not perform a full task switch mid-preemption nest. They request a PendSV; the NVIC runs PendSV when interrupt priority allows, typically as the lowest priority exception, after nested IRQs complete. That keeps ISR tail-chaining clean. PendSV is not NMI and not debug-only.

Question 48Real-time scheduling, firmware lifecycle and dependable state

Under rate-monotonic scheduling (RMS) with implicit deadlines equal to periods, how are static priorities assigned?

  1. Longer period gets higher priority
  2. Shorter period gets higher priority Correct answer.
  3. All tasks share one priority and run FIFO only
  4. Priority equals stack size in bytes

Explanation

RMS is a fixed-priority policy: the task with the shortest period (highest rate) gets the highest priority. That is optimal among static-priority uniprocessor schemes for independent periodic tasks under standard assumptions. FIFO-only or stack-size priority are not RMS.

Question 49Real-time scheduling, firmware lifecycle and dependable state

A function is reentrant if:

  1. It can be invoked concurrently (for example from two tasks or a task and an ISR) without corrupting shared state, typically by using only stack data or proper synchronization Correct answer.
  2. It always calls malloc for every local
  3. It disables the watchdog as its first line
  4. It may use unsynchronized global buffers freely

Explanation

Reentrancy means overlapping invocations do not interfere. That requires no unsynchronized static/global buffers and care with hardware. malloc in every call is neither necessary nor sufficient. Disabling the watchdog is unrelated. Unsynchronized globals are the usual reason a function is not reentrant.

Question 50Real-time scheduling, firmware lifecycle and dependable state

A short critical section that must not be preempted by an ISR on a bare-metal MCU is commonly implemented by:

  1. Printing a log line
  2. Busy-waiting on a mutex that the ISR also takes
  3. Disabling interrupts (or raising BASEPRI) around the shared update, then restoring the previous mask Correct answer.
  4. Calling malloc

Explanation

On bare metal, mutual exclusion with ISRs is often interrupt masking for a few instructions. RTOS mutexes cannot be taken in ISRs. Logging and malloc are slow and may themselves need locks. Keep critical sections short to bound interrupt latency.