Basic Computer Structure and Microprocessors
Architecture
A microprocessor contains the arithmetic logic unit, the control unit and registers. Von Neumann machines share one memory for data and instructions; Harvard machines use separate paths, allowing instruction fetch and data access simultaneously. The program counter holds the address of the next instruction, the instruction register holds the instruction being executed, and the status register holds flags. Buses carry addresses out, data in both directions, and control signals.
The cycle
Fetch, decode, execute: the processor reads the instruction from memory, works out what it means, then performs it. Interrupts let peripherals get attention: the processor saves context and jumps to a handler. Direct memory access moves blocks without the CPU. Cache reduces average memory access time, a watchdog timer resets a hung processor, and boot code lives in non-volatile memory because RAM loses its contents at power-off.
Traps
Confusing the program counter with the instruction register; claiming RISC instructions are more complex (they are simpler and mostly single-cycle); assuming more cache is always faster; forgetting that volatile memory is lost when power is removed. Another favourite: address bus width sets the maximum addressable memory - 16 bits gives 65 536 locations, which is 64 KB only if each location holds a byte.
Worked example
An 8-bit processor has a 16-bit address bus. It addresses 2^16 = 65 536 locations; with one byte per location that is 64 KB. If its data bus is 8 bits wide, moving a 32-bit value takes four transfers. This arithmetic appears far more often than any instruction set detail.