TEE Engineer License key terms

A hardware-isolated processing area that keeps code and data confidential and integrity-protected from the rest of the system, including a compromised rich OS or hypervisor. Isolation is enforced below the software layer being defended.

The complete set of hardware and software components whose correct behavior the security of a system depends on. Shrinking the TCB is a primary design goal because every included component becomes a potential attack surface.

A structured description of assets to protect, adversaries and their capabilities, trust boundaries, and the attacks considered in and out of scope. It defines what a TEE claim means and what it explicitly does not cover.

A line in the system where data or control passes between components with different privilege or trust levels. Every crossing must validate inputs, because assumptions made on the trusted side are attacker-controlled on the other.

The sum of entry points through which an adversary can attempt to influence a system, such as interfaces, parsers, shared memory, and side channels. Larger attack surfaces increase the probability of exploitable flaws.

The highest-privilege firmware component on Arm systems that mediates switches between normal and secure worlds and owns the world-switch mechanism. Compromise of the monitor breaks the isolation guarantee entirely.

Arm's system-wide security architecture that partitions execution into a normal world and a secure world, with bus-level filtering of accesses. It provides isolation primitives on which a TEE such as OP-TEE is built.

The transition between normal-world and secure-world execution, performed by the secure monitor with register state saved and restored. The switch path is security-critical because it handles state from an untrusted world.

An open-source TEE implementation for Arm TrustZone, comprising a secure-world OS, a normal-world driver, and a client library. It is widely used for research, product prototypes, and as a reference implementation.

A protected execution context, typically in Intel SGX or similar architectures, whose memory is encrypted and access-controlled by the CPU. Code and data inside remain confidential even to the operating system and hypervisor.

The protected physical memory region in Intel SGX where enclave pages reside, encrypted and integrity-checked by the CPU's memory encryption engine. Pages are loaded and evicted under hardware control.

An immutable, implicitly trusted component from which all subsequent trust is derived, such as boot ROM or a hardware key. If the root of trust is compromised, every guarantee built above it collapses.

A boot process that verifies cryptographic signatures on each stage before executing it, refusing to run unauthorized code. It enforces a policy of only approved firmware and operating system components.

A sequence in which each boot stage verifies the authenticity of the next before handing over control, anchored at a hardware root. A break at any link invalidates assurance for all later stages.

A boot process that records cryptographic hashes of loaded components into tamper-evident storage, typically a TPM's platform configuration registers. Unlike secure boot, it records rather than blocks, enabling later attestation.

A TPM register that accumulates measurements by extending, where each new value is hashed together with the previous one. The final value commits to the full sequence of measurements taken.

A protocol in which a device proves to a remote party, using hardware-backed keys, which software it is running and that it resides in a genuine TEE. The verifier checks a signed quote against trusted reference values.

A signed attestation structure, as produced by Intel SGX or a TPM, binding a measurement of the running environment to a hardware-protected key. The verifier validates the signature chain and compares measurements to policy.

A private key, held inside hardware and never exportable, used to sign attestation evidence so a verifier can confirm the platform's identity and state. Its certificate chain terminates at the silicon vendor.

Encrypting data with a key bound to a specific platform or enclave measurement so that only the same trusted environment can decrypt it later. It protects secrets at rest outside the TEE.

Generating keys deterministically from a root secret and context information such as a device identity or software measurement. It avoids storing many keys and lets access be tied to platform state.

A program that runs inside a TEE and exposes a narrow interface to untrusted clients, handling sensitive data such as keys or biometrics. Its security depends on rigorous input validation at the boundary.

A display and input path controlled by the TEE so that a user can enter secrets such as a PIN without the rich OS observing or altering them. The normal-world OS must be locked out during the interaction.

A buffer accessible to both a trusted application and an untrusted client for passing data across the isolation boundary. It must be treated as hostile and validated for size, alignment, and content on every use.

Protecting data in use by executing workloads inside hardware-isolated environments, extending encryption from data at rest and in transit to data being processed. It targets threats from cloud operators and infrastructure compromise.

A virtual machine whose memory and register state are protected by hardware from the hypervisor and host operator. Attestation lets a guest owner verify the platform before releasing secrets to the workload.

Extracting secrets by observing indirect physical or timing effects such as cache behavior, execution time, or power consumption, rather than by breaking cryptography. TEEs are not immune because they share hardware resources.

Leaking data through speculative execution whose results are architecturally discarded but leave observable traces in caches or buffers. Variants such as Meltdown and Spectre cross TEE boundaries on affected processors.

Information exposure caused by CPU implementation details, including caches, branch predictors, and prefetchers, that are not part of the architectural state. Mitigations are often partial and platform-specific.

Deliberately disturbing voltage, clock, or electromagnetic conditions to make a processor skip instructions or corrupt checks. It can defeat secure boot verification or key handling on poorly protected hardware.

Building an exploit from short instruction sequences already present in executable memory, chained via manipulated return addresses. It bypasses non-executable memory protections and is a common TEE attack technique.

A standards body whose specifications define TEE internal APIs, trusted application lifecycles, and secure element management. Certification programs test conformance and provide a common vocabulary across vendors.

An international framework for specifying and evaluating IT security, using protection profiles and evaluation assurance levels. TEE products are often certified under it to demonstrate independently assessed security properties.

Independent assessment by an accredited laboratory that a product meets a defined security standard or protection profile. It gives buyers evidence but is scoped to a specific version and configuration.

A tamper-resistant device that stores keys and performs cryptographic operations without exposing key material. It is often paired with a TEE to protect long-term secrets that must survive beyond a single enclave.

Information actively being processed in memory or registers, as distinct from data at rest and in transit. Protecting it is the specific problem confidential computing and TEEs address.

Privileged boot and runtime code, such as Arm Trusted Firmware, that establishes the secure world and implements the monitor. Its correctness underpins every isolation property above it.