Computer Organization: CPU, Memory Hierarchy and Data Representation
What the exam tests
Computer organization tests the CPU and memory hierarchy, data representation and logic. Expect fetch–decode–execute sequencing, register roles, RISC/CISC trade-offs, cache behavior, secondary storage comparisons, OS functions and binary arithmetic.
Core rules
- The CPU fetches an instruction using the program counter (PC) and memory address register (MAR), stores it in the memory data register (MDR) and instruction register (IR), decodes it in the control unit, then executes it in the ALU.
- Cache is fast SRAM close to the CPU; it exploits locality. Virtual memory uses secondary storage to extend apparent RAM, but is much slower.
- RISC uses simple fixed-length instructions and many registers; CISC uses complex variable-length instructions. Pipelining overlaps stages but hazards can stall it.
- Two's complement represents signed integers; in n bits the range is -2^(n-1) to 2^(n-1)-1.
- Floating point stores sign, biased exponent and normalized mantissa; precision is limited, so rounding error is normal.
Worked example
Compute -5 + 7 in 8-bit two's complement. +5 = 00000101, so -5 = invert (11111010) + 1 = 11111011. Add 00000111: 11111011 + 00000111 = 1 00000010. Discard the carry out; result 00000010 = +2. Reasoning: the range is -128 to +127; overflow occurs only when two same-sign operands produce an opposite-sign result, which does not happen here.
Traps
Confusing MAR (address) with MDR (data); treating cache as secondary storage; forgetting the exponent bias; reversing sign-and-magnitude and two's complement; assuming more RAM fixes all performance problems; ignoring pipelining hazards.