ESE Prelims Electrical common mistakes
ESE Prelims Electrical · Understand the traps and how to avoid them.
Applying the voltage-divider formula directly to a circuit that also has a current source or a load branch, instead of first reducing the network with source transformation or nodal analysis.
Candidates memorise the two-resistor divider pattern from basic circuit courses and pattern-match it to any resistor pair, ignoring that a parallel load or an ideal current source changes the topology and that the divider result only holds for a series string across an ideal voltage source.
What to do instead
Before substituting numbers, redraw the circuit and mark every node; confirm the two resistors are truly in series with nothing else connected at their junction. If a load or source taps the junction, switch to nodal analysis or Thevenin reduction. Practise ten mixed-source networks where the divider formula is deliberately wrong and check your answer by verifying KCL at each node.
Computing the Thevenin resistance by short-circuiting the load but leaving dependent sources active, or by killing independent sources and then mistakenly killing dependent sources too.
Textbook phrasing 'turn off all sources' is remembered without the qualifier that dependent sources must stay live and are handled with a test source; candidates then get a resistance that is simply the series-parallel combination and never notice the mismatch.
What to do instead
Adopt a fixed checklist: (1) remove the load, (2) kill only independent sources, (3) if any dependent source remains, apply a 1 V test source at the terminals and compute R = V/I, (4) cross-check by short-circuit current. Drill at least five networks containing a controlled source until the test-source step becomes automatic.
Treating the synchronous machine's V-curve or the transformer's equivalent circuit as if the magnetising branch sat on the load side, or drawing the phasor diagram with the wrong reference, leading to sign errors in regulation and power-angle calculations.
The approximate equivalent circuit is convenient and candidates stop tracking which quantities are referred to which side; with the magnetising branch moved, no-load current and copper loss get attributed to the wrong element, and phasor angles come out with reversed signs.
What to do instead
Always state the referral side and the reference phasor at the top of the working. For transformers, draw the exact equivalent circuit first, then justify any approximation explicitly. For synchronous machines, fix terminal voltage as reference and derive the internal emf from E = V + jXsI before computing regulation; verify the sign of the power angle against whether the machine is generating or motoring.
Using the wrong formula for efficiency or regulation because slip, load fraction, and power factor were substituted into the expression for a different operating point (for example using full-load copper loss at half load).
Induction motor and transformer efficiency peaks near but not at full load, and candidates plug rated copper loss into part-load expressions; similarly, regulation is computed with rated current when the question specifies a fraction of load at a given power factor.
What to do instead
Write the general expression with the load fraction x explicit: copper loss scales as x squared, output as x times rated kVA times power factor. Solve maximum-efficiency conditions by differentiating or by the equality of variable and constant losses, and state the condition before substituting. Re-read the stem and underline the specified load fraction and power factor.
Performing per-unit conversion by dividing by base voltage only, or mixing bases for different sections of a network separated by a transformer, without referring impedances across the transformer.
Per-unit analysis is taught quickly and candidates forget that the base voltage changes across each transformer according to its turns ratio, and that base impedance is V squared over S with consistent units.
What to do instead
Set up a base table first: choose S base once, then fix V base in each voltage level by propagating through transformer ratios. Convert every impedance with Z pu = Z actual times S base over V base squared before combining. Check that all per-unit voltages lie in a plausible range (roughly 0.9 to 1.1) as a sanity test.
Solving load flow or fault-level questions by assuming nominal voltage at every bus, or by ignoring the prefault current and load current in short-circuit calculations, when the question specifies actual operating conditions.
The flat-start assumption is a computational convenience, not a physical result; candidates also apply the simple E/X formula for fault current without checking whether the problem asks for subtransient, transient, or steady-state values and which reactance applies.
What to do instead
Identify the fault type and the required reactance (subtransient for first-cycle, transient for a few cycles, synchronous for steady state) before computing. Use the specified prefault voltage and state whether load current is neglected. For load flow, remember that slack bus voltage is fixed while PV bus voltage magnitude is fixed and reactive power floats; check that the specified quantities match the bus type.
Reading a Bode plot's corner frequency as the gain crossover frequency, or applying a phase margin formula without converting the magnitude to decibels and back correctly.
Both features appear on the same plot and candidates conflate the frequency where gain crosses 0 dB with the break frequency of a pole; decibel conversion errors (20 versus 10 log) also shift the crossover estimate.
What to do instead
Annotate the plot explicitly: mark the 0 dB line, the corner frequencies, and the phase at the gain crossover. Compute gain margin at the phase crossover (phase equals minus 180 degrees) and phase margin at the gain crossover, never the reverse. Re-derive the asymptotic slope change at each corner before reading values, and verify with the transfer function substituted at the candidate frequency.
Choosing an instrument or meter range without accounting for loading effect, and reporting a measured value with more significant figures than the instrument's accuracy justifies.
Candidates focus on the reading and forget that a voltmeter's finite resistance loads the circuit and an ammeter's resistance drops voltage; they also treat a 3.5-digit display as if it gave four-digit accuracy.
What to do instead
Before measuring, compare meter input impedance with the circuit impedance and estimate the loading error; for a voltmeter, the error fraction is roughly circuit resistance over meter resistance. Apply the specified accuracy class as a percentage of full-scale reading, not of the indicated value, and round the final answer to the precision the instrument supports. State the uncertainty explicitly.
Designing combinational logic by writing a truth table and then minimising with a Karnaugh map without checking for static hazards, or implementing a Boolean expression in a form that needs more gates than necessary because De Morgan's law was not applied.
Minimisation is taught as the end goal; hazard analysis and gate-count optimisation come later, and candidates also forget that NAND-only or NOR-only realisation requires converting the expression into the appropriate form.
What to do instead
After minimising, check adjacent 1-cells for a single-variable change that passes through a 0-cell (a static-1 hazard) and add the consensus term. Convert to NAND-only form by double-negating the expression so it becomes a product of sums of complemented products. Verify the final gate count and fan-in against any stated constraint before drawing.
Analysing a controlled rectifier or chopper by assuming the load current is continuous and the firing angle alone sets the output, when the load is highly inductive or discontinuous conduction occurs.
The continuous-conduction formula for average output voltage is simple and memorable, but it fails at large firing angles with resistive loads or light inductance, where the output voltage depends on extinction angle and the waveform clips at zero.
What to do instead
First determine the conduction mode from the load time constant and firing angle; for a resistive load the current is discontinuous whenever the firing angle exceeds the point where the supply voltage falls below the back emf. Use the full integral of the output waveform rather than the shortcut formula, and check whether a freewheeling diode clamps the output. Sketch the voltage and current waveforms for each case before computing.
Applying the final value theorem to a system whose poles lie in the right half-plane or on the imaginary axis, or confusing the Laplace transform's region of convergence with the transfer function's poles.
The final value theorem is presented as a shortcut and its validity condition (all poles of sX(s) strictly in the left half-plane) is easy to forget; candidates also treat the Fourier transform as always existing for a signal that grows.
What to do instead
Before invoking the final value theorem, list the poles of sX(s) and confirm none lie on or right of the imaginary axis. For stability questions, use the Routh-Hurwitz array on the characteristic polynomial. When a signal has no Fourier transform, state the Laplace region of convergence and note that the imaginary axis is excluded.
Using the Biot-Savart or Ampere's law formula without checking the symmetry required, or applying Gauss's law to a closed surface that does not enclose the charge distribution in the assumed symmetric way.
The integral forms are memorised as algebraic formulas, and candidates substitute a distance into the infinite-wire expression for a finite wire or off-axis point where the symmetry argument fails.
What to do instead
Before substituting, state the symmetry (cylindrical, planar, spherical) and the Gaussian surface or Amperian loop that exploits it. If the symmetry is absent, set up the integral explicitly. Check units and limiting behaviour (field should fall as 1/r for a line, 1/r squared for a point) as a quick validation of the result.
Spending disproportionate time on a single numerical question in the prelims, or skipping the general studies and engineering aptitude section entirely on the assumption that only technical marks matter.
The paper is a screening test with negative marking and a fixed cutoff; candidates over-invest in a hard circuit problem and then rush the aptitude section, losing easy marks and risking negative marking from guessed answers.
What to do instead
Set a per-question time budget before the exam and enforce it with a watch, marking and moving on after the budget expires. Attempt the aptitude and general-studies questions first to bank reliable marks, then return to technical numericals. Leave anything not confidently solved blank rather than guessing, given negative marking.