GATE CY case studies
GATE CY · Put your knowledge to work in context.
GATE 2026 is a national-level examination that assesses candidates on undergraduate-level subjects across Engineering, Technology, Science, Commerce, Arts, Architecture and Humanities. It is conducted by IIT Guwahati in collaboration with IISc Bengaluru and the other 22 IITs, on behalf of the National Coordination Board, Department of Higher Education, Ministry of Education, Government of India. The GATE CY case studies are 5 cases and about 4,349 words.
1Three Frames, One Benchmark: Replacement Policy and Where the Latency Really Goes
A team is profiling a 32-bit process on a machine deliberately restricted to three physical page frames, an artificial limit the kernel honours so that replacement behaviour can be studied in isolation. Page size is 4 KB, all pages start out non-resident, and the captured reference string is 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5.
966 words, about 5 min2A History That Passes the Precedence Test but Fails the Rollback Test
An online reservation service runs three transactions over data items A and B. Timestamps are T1 = 10, T2 = 20, T3 = 30, with lower meaning older.
798 words, about 4 min3Slicing a /21 and Surviving a 576-Byte Tunnel
An ISP hands a customer the address block 172.20.8.0/21 and requires it to be carved up for four VLANs and three router-to-router links. VLAN-A must seat 500 hosts, VLAN-B 250, VLAN-C 120, VLAN-D 60, and each of the three point-to-point links needs two usable addresses.
929 words, about 5 min4Three Registers, Seven Live Ranges: Choosing the Right Spill
A JIT compiler for a small register machine has three general-purpose registers free for allocation across a hot loop, after reserving two for temporaries. Liveness analysis over the loop body produces seven live ranges whose interference pairs are exactly: a–b, a–c, a–d, b–c, b–d, c–d, d–e, e–f, e–g, f–g; every other pair does not interfere.
856 words, about 4 min5Branch Predictor or Bigger L1: Reading CPI and Clock Together
A five-stage in-order core (IF, ID, EX, MEM, WB) runs at 1 GHz with an ideal CPI of 1.0 and no structural hazards. Profiling the target workload gives: 20% of dynamic instructions are conditional branches, 30% of those are mispredicted, and each misprediction flushes three cycles; 25% of instructions are loads, 10% of which miss in the 32 KB L1 and cost a further 15 cycles when serviced from L2.
800 words, about 4 min