Digital Logic
Digital Logic in GATE covers number representation, Boolean minimisation, combinational building blocks and sequential circuits, usually as 2–4 marks of crisp, verifiable questions. Almost every question is checkable by hand, so the marks come from care rather than insight.
Number representation
- Two's complement with n bits represents −2ⁿ⁻¹ to 2ⁿ⁻¹−1; negation is invert-all-bits plus one.
- IEEE 754 single precision: 1 sign bit, 8 exponent bits with bias 127, 23 fraction bits. Exponent 0 and 255 are reserved (zero/denormal and infinity/NaN).
Boolean minimisation
- K-map groups must be rectangular, contain 1, 2, 4, 8 … cells, and may wrap around edges and corners.
- Don't-care terms may be used to enlarge a group but never need to be covered.
- NAND and NOR are each functionally complete; a 4-input AND needs three 2-input NAND gates.
Sequential circuits
- A mod-N counter needs ⌈log₂N⌉ flip-flops; unused states require explicit reset logic.
- JK flip-flops exhibit race-around when J = K = 1 and the clock pulse is wider than the propagation delay.
Worked example
Encode −12.5 in IEEE 754 single precision. 12.5 = 1100.1₂ = 1.1001 × 2³. Sign = 1. Exponent = 127 + 3 = 130 = 10000010. Fraction = 1001 followed by zeros. The word is 1 10000010 1001000…0 = 1100 0001 0100 1000 0000 0000 0000 0000 = 0xC1480000.
Traps that cost marks
- Reading the block offset in words instead of bytes.
- Assuming every K-map grouping of four is valid when it is not a power-of-two rectangle.
- Forgetting that a don't-care cannot be the only cell covering a term.