Computer Organization and Architecture
This domain tests machine-level execution: instruction formats and addressing, datapath and control, pipelining, the memory hierarchy and I/O. Questions are quantitative - cache geometry, speedup, effective access time - so set up the calculation before touching the options.
Pipelining
- A k-stage pipeline ideally executes n instructions in k + (n−1) cycles, giving speedup nk/(k + n−1) → k.
- Hazards: structural (resource conflict), data (RAW, partly removed by forwarding), control (branch, mitigated by prediction or delay slots).
Memory hierarchy
- AMAT = hit time + miss rate × miss penalty.
- Direct-mapped cache: number of lines = cache size / block size; index bits = log₂(lines).
- Set-associative: sets = cache size / (block size × associativity).
- Write-through keeps memory coherent with high traffic; write-back needs a dirty bit but lowers traffic.
Addressing modes
- Immediate (operand in instruction), direct (address in instruction), indirect (address of address), register, register-indirect, indexed and base-relative - each changes the effective-address computation, not just the syntax.
Worked example
A 32-bit address machine has a 32 KB 4-way set-associative cache with 64-byte blocks. Sets = 32768 / (64 × 4) = 128, so the index field is 7 bits and the block offset is log₂64 = 6 bits. The tag is 32 − 7 − 6 = 19 bits. Total tag storage = 128 sets × 4 ways × 19 bits, plus valid/dirty bits if present.
Traps that cost marks
- Using word offset where the question states byte offset.
- Assuming every data hazard stalls the pipeline - forwarding removes many.
- Believing a TLB hit implies a cache hit; the TLB translates addresses, the cache supplies data.