Karnataka II PUC Electronics (KSEAB) study materials
Karnataka II PUC Electronics (KSEAB) study resources

Karnataka II PUC Electronics (KSEAB): Bipolar Junction Transistors and Field-Effect Transistors

Karnataka II PUC Electronics (KSEAB) · Work through your exam, one topic at a time.

All guide sections

Bipolar Junction Transistors and Field-Effect Transistors

What this domain tests

BJT construction and action, the three configurations, biasing and Q-point stability, plus JFET and MOSFET operation with transconductance and pinch-off. Expect questions on α-β relations, why voltage-divider bias is preferred, and comparisons between BJT and FET.

Core rules

  • Emitter is heavily doped, base thin and lightly doped, collector moderately doped and physically largest to dissipate heat.
  • Active region: emitter junction forward biased, collector junction reverse biased - the only region used for amplification.
  • Current relations: Ie = Ic + Ib, α = Ic/Ie, β = Ic/Ib, and β = α/(1 − α).
  • Cut-off means both junctions reverse biased (switch OFF); saturation means both forward biased (switch ON). In saturation Ic is set by the external circuit, not by βIb.
  • DC load line joins Vcc/Rc on the current axis to Vcc on the voltage axis; the Q point is the intersection with the output characteristic.
  • Voltage-divider bias is the standard because its Q point is almost independent of β spread and temperature.
  • JFET: gate junction reverse biased, depletion region pinches the channel; IDSS is the drain current at Vgs = 0 and Vp is pinch-off voltage; gm = ΔId/ΔVgs at constant Vds. FETs give very high input impedance and low noise but lower gm and gain than a BJT.

Worked example

A silicon BJT has β = 100 and Ib = 20 µA in the active region. Ic = βIb = 2 mA, Ie = Ic + Ib = 2.02 mA, so α = Ic/Ie = 0.990. Check: α/(1 − α) = 0.990/0.010 = 99, consistent with β = 100 within rounding.

Traps that cost marks

  • Applying Ic = βIb inside saturation.
  • Confusing α (always below 1) with β (usually above 20).
  • Reversing the bias conditions for active and saturation regions.
  • Treating the JFET gate as forward biased; it must stay reverse biased for normal operation.