Digital Electronics and Logic Circuits
What this domain tests
Number systems and codes, logic gates and truth tables, Boolean algebra and simplification, combinational blocks (adders, multiplexers, decoders) and sequential blocks (flip-flops, registers, counters).
Core rules
- Binary to decimal uses positional weights; BCD uses four bits per decimal digit and is not the same as binary beyond 9; hexadecimal groups four bits at a time.
- De Morgan: (A·B)′ = A′ + B′ and (A + B)′ = A′·B′. NAND and NOR are universal because each can realise NOT, AND and OR.
- A NAND or NOR gate with its inputs tied together behaves as an inverter.
- K-map grouping uses 1, 2, 4, 8 or 16 adjacent cells in powers of two; overlapping groups are allowed and each group must be as large as possible. SOP form groups the 1s, POS form groups the 0s.
- Half adder: Sum = A ⊕ B, Carry = A·B. Full adder adds a carry-in and is built from two half adders plus an OR gate.
- SR latch is level sensitive; JK removes the invalid state but has race-around, cured by master-slave or edge triggering; D flip-flop is a data latch; T flip-flop toggles.
- A mod-N counter needs n flip-flops where 2ⁿ ≥ N; unused states are cleared by feedback reset.
Worked example
Simplify Y = Σm(0,1,3) for variables A, B. Minterms are A′B′ (0), A′B (1) and AB (3). Group m0 with m1 to give A′, and m1 with m3 to give B. The simplified expression is Y = A′ + B, which uses one inverter and one OR gate instead of three AND terms.
Traps that cost marks
- Misapplying De Morgan by changing the sign without complementing each literal.
- Forgetting that only power-of-two group sizes are legal in a K-map.
- Reading bit strings from the wrong end (LSB versus MSB).
- Treating BCD 1001 as decimal 9 but then continuing as if 1010 were valid BCD.