Analog and Digital Electronics
What the exam tests
Analog and Digital Electronics tests op-amp configurations, diode/BJT circuits, logic gates, flip-flops, counters, and data converters. The exam favours circuit-level reasoning and timing behaviour over memorized pin diagrams.
Core rules
- Ideal op-amp: infinite gain, infinite input impedance, zero output impedance; with negative feedback, virtual short holds at the inputs.
- Inverting amplifier gain = −Rf/Rin; non-inverting gain = 1 + Rf/R1. Slew rate limits large-signal high-frequency response.
- BJT regions: cutoff, active, saturation. For switching, drive hard into saturation; for amplification, stay in active region.
- Digital logic: Karnaugh maps minimize SOP/POS; NAND and NOR are universal gates.
- Flip-flops are edge-triggered; setup and hold times must be met. ADC resolution = VFS/(2^n − 1); conversion time limits sampling rate.
Worked example
An inverting op-amp has Rin = 2 kΩ, Rf = 20 kΩ, input 0.2 V, and ±12 V supplies. Gain = −20/2 = −10, so ideal output = −2 V. The feedback node is a virtual ground, so input current = 0.2/2 kΩ = 0.1 mA; the same current flows in Rf, producing 2 V drop. The output stays within the rails, so the op-amp remains linear.
Traps
Do not apply virtual short when there is no negative feedback. Do not confuse saturation with cutoff. In sequential circuits, asynchronous clear dominates clocked operation. In ADCs, 8-bit resolution does not mean 8-bit accuracy; noise and reference error reduce effective bits.