Microprocessors, Microcontrollers and Embedded Systems
What the exam tests
Microprocessors, Microcontrollers and Embedded Systems tests architecture, addressing modes, interrupts, timers, serial communication, and interfacing. MPPSC SES typically draws on 8085 and 8051 fundamentals and basic embedded design.
Core rules
- 8085 has an 8-bit data bus and 16-bit address bus, with AD0–AD7 multiplexed; ALE latches the lower address byte.
- 8051 has separate program and data memory spaces, four register banks, two timers, and five interrupt sources. Port 0 needs external pull-ups when used as general-purpose I/O.
- Machine cycle length depends on crystal frequency; for 8051, 12 clock cycles per machine cycle in classic mode.
- Interrupts have priority; timer overflow and serial interrupts are flag-based. ISRs should be short and use volatile variables for shared data.
- Memory-mapped I/O uses normal load/store instructions; port-mapped I/O uses dedicated instructions.
Worked example
An 8051 uses a 12 MHz crystal, so one machine cycle is 12/12 MHz = 1 μs. In timer mode 1 (16-bit), the timer counts up and overflows at 65536. For a 50 ms delay, required counts = 50,000. Reload = 65,536 − 50,000 = 15,536 = 0x3CB0. Load TH0 = 0x3C and TL0 = 0xB0, then start the timer and wait for TF0.
Traps
Do not confuse crystal frequency with machine-cycle frequency. Do not assume 8051 ports are symmetric: port 0 is open-drain. Do not forget that interrupt latency and ISR execution add to timer delay. In 8085, forgetting ALE demultiplexing causes address/data bus contention.