Ripple Counter Feeding a Decoder and Comparator
A student prototype of a batch counter uses a 74LS93 4-bit ripple counter clocked at 1 MHz. Outputs QA–QD drive a 74LS47 BCD-to-seven-segment decoder for a common-anode display, and also a 74LS85 comparator set to detect decimal 12, whose output fires a retriggerable 1 ms monostable that holds a relay on through an NPN transistor. Each 74LS flip-flop has tpd = 20 ns; the decoder adds 25 ns and the comparator 25 ns. Bench DC ratings: IOH = 0.4 mA, IOL = 8 mA, IIH = 20 µA, IIL = 0.4 mA. The display uses common-anode LEDs with Vf = 1.9 V and a nominal 12 mA per segment from +5 V; the decoder's V_OL is about 0.4 V. Two segments share one 220 Ω resistor. During the test the relay clicks at counts other than 12, and those two segments look noticeably dimmer than the rest.
1. The counter's QD output drives the decoder's D input, the comparator's A input, and a test-point buffer. Check the DC fan-out and state whether the loading is acceptable.
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Compute both current directions and take the smaller limit:
Sink side: IOL / IIL = 8 mA / 0.4 mA = 20 Source side: IOH / IIH = 0.4 mA / 20 µA = 20
DC fan-out = min(20, 20) = 20 LS loads.
QD actually drives three loads (decoder D, comparator A, buffer), which is 15 % of the limit, so DC loading is fine. That also tells us the wrong-count problem is not a drive-strength issue: the counter is not being dragged out of its logic levels. Two things still deserve a check: at 1 MHz the capacitive load and wiring inductance matter more than DC fan-out, so keep the clock and QD traces short; and the decoder's segment outputs drive LEDs, not LS inputs, so they must be checked against the 74LS47's own sink rating rather than against fan-out.
2. Explain, with the binary sequence, why the relay can pull in at a count other than 12, and give a practical fix.
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In a ripple counter the flip-flops change in sequence, so intermediate codes appear on the outputs for tens of nanoseconds. Going from 13 (1101) to 14 (1110), QA falls first and gives 1100 = 12 before QB and QC settle. With 4 stages the skew can be up to about 4 × 20 = 80 ns, plus 25 ns comparator delay, i.e. roughly 105 ns of false code 12 on every such transition.
105 ns is far shorter than the 1 ms monostable period, but the monostable is retriggerable: every false 12 re-arms it, so the relay eventually stays energised when the counter passes through that transition. The count itself is correct; the decoding is not qualified.
Fixes, in order of preference: clock the count into a 74LS175 register with the same clock and decode/compare the registered value; or replace the 74LS93 with a synchronous counter such as the 74LS163, where all outputs change within one tpd; or strobe the comparator output a few hundred nanoseconds after each clock edge. A comparator alone cannot distinguish a settled code from a transient one.
3. Calculate the correct segment resistor and explain why the two shared segments are dim.
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The resistor must drop the supply minus the LED forward voltage and the decoder's output-low voltage:
R = (5 − 1.9 − 0.4) / 12 mA = 2.7 / 0.012 = 225 Ω → use 220 Ω
With 220 Ω the current is (5 − 1.9 − 0.4)/220 ≈ 12.3 mA, essentially the design value.
When two segments share one 220 Ω resistor, the resistor carries the sum of both currents, so its drop is larger and each LED sits at a lower current, roughly half - about 6 mA each - which the eye reads as clearly dimmer. Unequal Vf between the two LEDs also makes them share unevenly. The fix is one resistor per segment (seven in all), which also keeps the decoder's V_OL from rising with total sink current. Keep the resistor value fixed and change only the count of resistors.