Digital Electronics and Logic Design
What this domain tests
Digital electronics questions cover number systems, Boolean algebra, logic gates, combinational design, flip-flops, counters, registers, and basic data conversion. Expect simplification and timing-based conceptual items.
Core concepts
- De Morgan's theorems: (A·B)' = A' + B' and (A + B)' = A'·B'. NAND and NOR are universal gates because either can implement all basic gates.
- SOP and POS forms map directly to AND-OR and OR-AND networks. A Karnaugh map groups 1s in powers of two to remove variables.
- Combinational circuits have no memory: adders, multiplexers, decoders, encoders. Sequential circuits store state: latches, flip-flops, counters, shift registers.
- A D flip-flop copies D to Q at the clock edge. A JK flip-flop toggles when J = K = 1. A ripple counter has cumulative propagation delay; a synchronous counter clocks all stages together.
- Setup time is the interval before the clock edge during which data must be stable; hold time is the interval after the edge.
Worked example
Simplify Y = AB + AB' + A'B. First, AB + AB' = A(B + B') = A. Then Y = A + A'B. Using A + A'B = A + B, the result is Y = A + B. A K-map gives the same answer.
Traps
Do not confuse a latch with an edge-triggered flip-flop. NAND is not AND followed by inversion in every context: check the bubble. Unused CMOS inputs must not float. In ripple counters, decode states only after settling.
Key points
- NAND and NOR are universal gates.
- K-map groups must be powers of two.
- D flip-flop: Q follows D at the clock edge.
- JK with J = K = 1 toggles.
- Setup and hold times constrain clocked data.