Computer Fundamentals and Organization
What this domain tests
This section checks whether you can reason about how a computer is put together: functional units, the stored-program model, buses, the memory hierarchy, and number systems and data representation. Questions are usually short calculations or one-line conceptual distinctions.
Functional units and the instruction cycle
A computer has five functional units: input, memory, the arithmetic logic unit (ALU), the control unit (CU) and output; the ALU plus CU form the CPU. In the von Neumann model, instructions and data share one memory, so the CPU loops through fetch, decode and execute. The program counter (PC) holds the address of the next instruction, the memory address register (MAR) carries that address to memory, and the fetched word goes to the memory buffer register (MBR) and then to the instruction register (IR).
Sizing rules that appear in questions
- Number of addressable locations = 2 raised to the address-bus width.
- Word size is fixed by the data bus or MBR width, not the address bus.
- 1 KiB = 1024 bytes; 1 MiB = 1024 KiB.
- Hierarchy, fastest to slowest: registers, cache, RAM, SSD or disk, tape.
Worked example
A processor has a 20-bit address bus and a 16-bit word. How much memory can it address? Locations = 2^20 = 1,048,576 = 1 M words. Each word is 2 bytes, so capacity = 1 M x 2 B = 2 MiB. The reasoning: the address bus fixes the count of locations; the word size converts that count into bytes.
Traps that cost marks
- Answering 2^20 bytes when a word is 16 bits.
- Mixing decimal prefixes (KB = 1000 B in storage marketing) with binary prefixes (KiB = 1024 B).
- Confusing the PC (address of the next instruction) with the IR (the current instruction).
- Assuming a higher clock alone means a faster machine; cycles per instruction and instruction mix also matter.