Digital Electronics and Computer Architecture
What this domain tests
This domain covers number systems and codes, Boolean algebra and logic gates, combinational and sequential circuits, and processor architecture topics such as pipelining, cache mapping, RISC versus CISC and addressing modes.
Number systems and codes
Binary, octal, hexadecimal and BCD conversions are routine. Two's complement represents negatives and removes the double zero of one's complement; the range of an n-bit signed number is minus 2^(n-1) to 2^(n-1) minus 1, so 8 bits give minus 128 to 127. Gray code changes exactly one bit between successive values.
Boolean algebra and circuits
NAND and NOR are universal gates. De Morgan's laws allow conversion between AND and OR forms, and Karnaugh maps minimise sum-of-products expressions by grouping 1s in blocks of 1, 2, 4 or 8 with wraparound allowed. Combinational circuits include adders, multiplexers, decoders and encoders; sequential circuits include flip-flops, registers and counters. A half adder gives Sum = A XOR B and Carry = A AND B; a full adder gives Sum = A XOR B XOR Cin.
Worked example
Simplify F(A, B, C) = sigma (1, 3, 5, 7). Write minterms: 001, 011, 101, 111. In every one of them C = 1 and A and B vary across all four combinations. A K-map group of four cells therefore eliminates both A and B, leaving F = C.
Architecture points
Pipelining overlaps instruction stages and gives a speedup approaching the number of stages for long instruction streams, limited by hazards. Cache mapping is direct, fully associative or set-associative, with associativity reducing conflict misses. RISC uses simple fixed-length instructions and many registers; CISC uses complex variable-length instructions. Addressing modes include immediate, direct, indirect, register, indexed and relative.
Traps that cost marks
- Grouping K-map cells in threes or fives; only powers of two are legal.
- Forgetting the one's complement dual zero.
- Confusing multiplexer with decoder, or latch with flip-flop.
- Ignoring pipeline hazards when quoting ideal speedup.