Synchronous buck saturating at high line
An isolated telecom converter steps 48 V nominal (36–60 V) down to 12 V at 5 A using a synchronous buck at 200 kHz. The chosen inductor is 22 µH with 6.0 A saturation and 30 mΩ DCR; the output capacitor is 100 µF with 20 mΩ ESR. The high-side and low-side MOSFETs are 25 mΩ each, with 20 nC gate charge and 20 ns transition times; the gate drive is 10 V. The board must meet a 100 mV output-ripple limit and a 90% efficiency target over the full input range. In the first prototype, the current limit trips at full load with 60 V input, while operation at 36 V input looks acceptable. The layout has a 15 nH parasitic power-loop inductance and a 2 cm loop area.
1. Compute the worst-case inductor ripple and peak current, explain the 60 V failure, and propose a component change with justification.
Read the worked answer
Duty cycle at 60 V D = 12/60 = 0.20.
Ripple ΔIL = (Vin − Vout) × D / (L × f) = (60 − 12) × 0.20 / (22 µH × 200 kHz) = 9.6 / 4.4 = 2.18 A.
Peak current I_peak = 5 + 2.18/2 = 6.09 A, which exceeds the 6.0 A saturation rating. The inductance collapses, current rises rapidly and the current limit trips. At 36 V, D = 0.333 and ΔIL = 1.82 A, giving a peak of 5.91 A - still only 0.09 A below saturation, so there is effectively no margin at either extreme.
Fix
- 33 µH: ΔIL = 9.6/(33 µH × 200 kHz) = 1.45 A, peak = 5.73 A.
- 47 µH: ΔIL = 9.6/(47 µH × 200 kHz) = 1.02 A, peak = 5.51 A.
- Alternatively raise f to 300 kHz with 33 µH: ΔIL = 9.6/(33 µH × 300 kHz) = 0.97 A.
Choose 47 µH at 200 kHz for the largest saturation margin, or 33 µH at 300 kHz if size matters. Recheck DCR loss, because a larger inductor usually has higher resistance, and check that the higher switching frequency does not push switching loss past the efficiency target.
2. Estimate the output ripple at 60 V input and decide whether the 100 µF capacitor meets the 100 mV limit.
Read the worked answer
Ripple components With ΔIL = 2.18 A:
- ESR term = ΔIL × ESR = 2.18 × 0.020 = 43.6 mV.
- Capacitive term = ΔIL / (8 × f × C) = 2.18 / (8 × 200 kHz × 100 µF) = 2.18/160 = 13.6 mV.
- Estimated total ≈ 57 mV, below the 100 mV limit.
Judgement The capacitor is adequate at room temperature, but the margin is only about 43 mV and ESR rises sharply at low temperature. A 20 mΩ ESR rating at 25 °C can double at −40 °C, pushing the ESR term toward 87 mV and the total close to the limit. Also, the 15 nH loop inductance and 2 cm loop area add high-frequency spikes that a bulk capacitor with 20 mΩ ESR does not absorb.
Recommendation Keep the 100 µF bulk capacitor but add a small ceramic capacitor of 1–10 µF close to the MOSFET pair to handle the switching spike, and verify ripple at low temperature and at 60 V input. If the measured low-temperature ripple exceeds 80 mV, increase the bulk capacitance or lower ESR rather than relying on the nominal 57 mV estimate.
3. Estimate full-load efficiency at 60 V input and identify the dominant loss. Does the design meet the 90% target?
Read the worked answer
Output power Pout = 12 × 5 = 60 W.
Loss estimate at 60 V
- High-side conduction: D × I² × R = 0.20 × 25 × 0.025 = 0.125 W.
- Low-side conduction: 0.80 × 25 × 0.025 = 0.500 W.
- Inductor DCR: 25 × 0.030 = 0.750 W.
- Switching: 0.5 × Vin × I × (tr + tf) × f = 0.5 × 60 × 5 × 40 ns × 200 kHz = 1.20 W.
- Gate drive: 2 × 20 nC × 10 V × 200 kHz = 0.08 W.
- Total ≈ 2.66 W.
Efficiency η = 60/(60 + 2.66) = 95.8%.
The 90% target is comfortably met. The dominant loss is switching, about 1.2 W, followed by inductor DCR at 0.75 W. If the inductor is changed to 47 µH, DCR may rise and reduce the margin; if the frequency is raised to 300 kHz for ripple control, switching loss rises to about 1.8 W and efficiency falls to roughly 94.5%, still above target but with less margin. The layout should also be tightened because the 15 nH loop inductance increases voltage ringing and effective switching loss.