Safety Instrumented Systems and Safety Lifecycle
Safety instrumented systems are engineered around safety functions, not just devices. The safety lifecycle runs from hazard/risk assessment and allocation through design, verification, installation, validation, operation, proof testing, modification, and decommissioning. A safety instrumented function (SIF) comprises sensor(s), logic solver, and final element(s); its SIL applies to the whole loop. Low-demand mode uses PFDavg, while high-demand/continuous mode uses PFH. Reliability vocabulary matters: random vs systematic failure, safe detected/undetected, dangerous detected/undetected, common cause, and systematic capability. Hardware fault tolerance, safe failure fraction, diagnostics, proof-test interval, and proof-test coverage determine achieved integrity. SIL is not a property you can read from a single instrument; it is a claim about the function and its verification.
Traps include crediting a BPCS interlock as independent when it shares sensors or final elements, confusing SIL with component integrity, ignoring final-element failure rates, and treating a bypass as permanent design. Also distinguish SIS from SIF, and proof test from partial stroke test.
Worked example: a 1oo1 transmitter has dangerous undetected failure rate λDU = 1×10−6/hour and a one-year proof-test interval (8,760 h). PFDavg ≈ λDU × TI/2 = 1×10−6 × 8,760/2 = 4.4×10−3, nominally SIL 2 (1×10−3 to 1×10−2). Rule of thumb: doubling proof-test interval doubles PFDavg, so test coverage and interval are design variables.